參數(shù)資料
型號(hào)： MESC-ST1
廠商： Lineage Power
英文描述： Enhanced Services Controller，Statistics Monitor - 65535 Connections(可統(tǒng)計(jì)檢測(cè)65535個(gè)連接的增強(qiáng)型服務(wù)控制器)
中文描述： 增強(qiáng)服務(wù)控制器，統(tǒng)計(jì)監(jiān)測(cè)- 65535連接（可統(tǒng)計(jì)檢測(cè)65535個(gè)連接的增強(qiáng)型服務(wù)控制器）
文件頁(yè)數(shù)： 26/31頁(yè)
文件大?。?/td> 182K
代理商： MESC-ST1
August 2000
MESC_ST1
MACRO
Data Sheet
Logic Design Solutions
26/28
1.9
FPGA Timing
The ORCA 3T125-7-BGA352 respect the following timing :
1.10
CPU interface
-
FPGA Clock_to_Out = 8 ns (refer to external clock).
-
FPGA Input setup time = 8 ns (refer to external clock).
-
FPGA Hold time = 1 ns (refer to external clock).
-
External Frequency = up to 17 MHz (58 ns period).
1.11
APC interface
-
FPGA Clock_to_Out = 8 ns (refer to external clock).
-
FPGA Input setup time = 8 ns (refer to external clock).
-
FPGA Hold time = 1 ns (refer to external clock).
-
External Frequency = 50 MHz (20 ns period).
1.12
SDRAM interface
-
FPGA Clock_to_Out = 8 ns (refer to external clock).
-
FPGA Input setup time = 4 ns (refer to external clock).
-
FPGA Hold time = 1 ns (refer to external clock).
-
External Frequency = 100 MHz (10 ns period).
1.13
SDRAM Device used
The SDRAM devices used have to respect the following features :
-
-
-
-
-
PC100-compliant
8 Meg x 16 organisation (in case of one device)
64ms, 4096-cycle refresh
CAS Latency = 2
Full page mode available
1.14
FPGA Configuration
The preferred FPGA configuration mode taking into account of the BGA 352 pinout are the following :
-
-
Master Serial Configuration
Slave Serial Configuration
Please refer to ORCA Series 3 FPGA data sheet for Configuration schematic details.
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