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參數(shù)資料
| 型號： | MESC-ST1 |
| 廠商： | Lineage Power |
| 英文描述： | Enhanced Services Controller，Statistics Monitor - 65535 Connections(可統(tǒng)計檢測65535個連接的增強(qiáng)型服務(wù)控制器) |
| 中文描述： | 增強(qiáng)服務(wù)控制器，統(tǒng)計監(jiān)測- 65535連接（可統(tǒng)計檢測65535個連接的增強(qiáng)型服務(wù)控制器） |
| 文件頁數(shù)： | 6/31頁 |
| 文件大?。?/td> | 182K |
| 代理商： | MESC-ST1 |
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August 2000
MESC_ST1
MACRO
Data Sheet
Logic Design Solutions
6/28
1.4
Functionnal Description
The MESC_ST1 Controller manages three set of statistics.
-
The first set is a
per PHY Port Statistics for up to 32 ports. This set of statistics is processed in the FPGA.
-
The second set of statistics is processed in the IE_SDRAM.
-
The third set of statistics is processed in the E_SDRAM.
1.4.1
The first set of statistics
There is two statistics in the first set of statistics :
Ingress Received Cells 16-bits Counter (for convenience called – phy_stat_0)
Egress Transmitted Cells 16-bits Counter (for convenience called - phy_stat_1)
The process of these statistics
is done in the FPGA.
The first bloc is a Connection Memory which contains the CPU programmed PHY Port to be monitored. Up to 32 ports can be
monitored.
The second bloc contains two statistic counters for up to 32 PHY ports.
When one match happen between the E.S.I. bus and the Connection Memory on a particular port, the two statistic counters of
this channel are updated according E.S.I. data.
If one statistic counter roll over, one interruption is generated and one status interrupt register is updated to inform the CPU.
When the CPU reads the statistic counters of a paricular PHY port, this will reset all the statistic counters associated to this
port.
Connection
Memory
32 PHY port
E.S.I. bus
CPU_Write
32 Ports
Stat. 0
Stat. 1
CPU_Read
Irq_ovf
Port match
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