參數(shù)資料
型號: MC68HC05JB4DWR2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PDSO28
封裝: SOIC-28
文件頁數(shù): 95/134頁
文件大?。?/td> 1305K
代理商: MC68HC05JB4DWR2
February 24, 1999
GENERAL RELEASE SPECIFICATION
MC68HC05JB4
16-BIT TIMER
MOTOROLA
REV 2
9-7
Writing to the OCRH before writing to the OCRL inhibits timer compares until the
OCRL is written. Reading or writing to the OCRL after reading the TSR will clear
the output compare ag bit (OCF).
Figure 9-8. Timer Output Compare Block Diagram
To prevent OCF from being set between the time it is read and the time the output
compare registers are updated, use the following procedure:
1.
Disable interrupts by setting the I bit in the condition code register.
2.
Write to the OCRH. Compares are now inhibited until OCRL is written.
3.
Read the TSR to arm the OCF for clearing.
4.
Enable the output compare registers by writing to the OCRL. This also
clears the OCF ag bit in the TSR.
5.
Enable interrupts by clearing the I bit in the condition code register.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
OCRH
R
OCRH7
OCRH6
OCRH5
OCRH4
OCRH3
OCRH2
OCRH1
OCRH0
$0016
W
reset:
UUUUUUUU
OCRL
R
OCRL7
OCRL6
OCRL5
OCRL4
OCRL3
OCRL2
OCRL1
OCRL0
$0017
W
reset:
UUUUUUUU
U = UNAFFECTED BY RESET
Figure 9-9. Output Compare Registers (OCRH, OCRL)
OCIE
OCRH ($0016)
16-BIT COUNTER
÷ 4
INTERNAL
(fOSC ÷ 2)
TIMER CONTROL REG.
TIMER
REQUEST
OUTPUT COMPARE
RESET
CLOCK
INTERRUPT
OCRL ($0017)
OCF
TIMER STATUS REG.
$0012
$0013
INTERNAL
($FFFC)
DATA
R/W
OCRH
R/W
OCRL
BUS
16-BIT COMPARATOR
(OCF)
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