參數(shù)資料
型號: MC68HC05JB4DWR2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PDSO28
封裝: SOIC-28
文件頁數(shù): 116/134頁
文件大小: 1305K
代理商: MC68HC05JB4DWR2
GENERAL RELEASE SPECIFICATION
February 24, 1999
MOTOROLA
UNIVERSAL SERIAL BUS MODULE
MC68HC05JB4
10-16
REV 2
10.4.4.2 Bit Stufng
In order to ensure adequate signal transitions, bit stufng is employed by the
transmitting device when sending a packet on the USB (see Figure 10-18 and
Figure 10-19). A 0 is inserted after every six consecutive 1’s in the data stream
before the data is NRZI encoded to force a transition in the NRZI data stream.
This gives the receiver logic a data transition at least once every seven bit times to
guarantee the data and clock lock. The receiver must decode the NRZI data,
recognize the stuffed bits, and discard them. Bit stufng is enabled beginning with
the Sync Pattern and throughout the entire transmission. The data “one” that ends
the Sync Pattern is counted as the rst one in a sequence. Bit stufng is always
enforced, without exception. If required by the bit stufng rules, a zero bit will be
inserted even if it is the last bit before the end-of-packet (EOP) signal.
Figure 10-18. Bit Stufng
IDLE
NRZI
ENCODED
DATA
BIT
STUFFED
DATA
RAW
DATA
STUFFED BIT
SYNC PATTERN
PACKET DATA
SYNC PATTERN
PACKET DATA
SYNC PATTERN
SIX ONES
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