參數(shù)資料
型號: MC68HC05JB4DWR2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PDSO28
封裝: SOIC-28
文件頁數(shù): 61/134頁
文件大小: 1305K
代理商: MC68HC05JB4DWR2
GENERAL RELEASE SPECIFICATION
February 24, 1999
MOTOROLA
INTERRUPTS
MC68HC05JB4
4-2
REV 2
NOTE
If more than one interrupt request is pending, the CPU fetches the vector of the
higher priority interrupt rst. A higher priority interrupt does not actually interrupt a
lower priority interrupt service routine unless the lower priority interrupt service
routine clears the I bit.
4.2
INTERRUPT PROCESSING
The CPU does the following actions to begin servicing an interrupt:
Stores the CPU registers on the stack in the order shown in Figure 4-1.
Sets the I bit in the condition code register to prevent further interrupts.
Loads the program counter with the contents of the appropriate interrupt
vector locations as shown in Table 4-1.
The return from interrupt (RTI) instruction causes the CPU to recover its register
contents from the stack as shown in Figure 4-1. The sequence of events caused
by an interrupt are shown in the ow chart in Figure 4-2.
$0020
(BOTTOM OF RAM)
$0021
$00BE
$00BF
$00C0
(BOTTOM OF STACK)
$00C1
$00C2
UNSTACKING
ORDER
n
CONDITION CODE REGISTER
5
1
n+1
ACCUMULATOR
4
2
n+2
INDEX REGISTER
3
n+3
PROGRAM COUNTER (HIGH BYTE)
2
4
n+4
PROGRAM COUNTER (LOW BYTE)
1
5
STACKING
$00FD
ORDER
$00FE
$00FF
TOP OF STACK (RAM)
Figure 4-1. Interrupt Stacking Order
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