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參數(shù)資料
| 型號： | MC68HC05JB4DWR2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 94/134頁 |
| 文件大?。?/td> | 1305K |
| 代理商： | MC68HC05JB4DWR2 |
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GENERAL RELEASE SPECIFICATION
February 24, 1999
MOTOROLA
16-BIT TIMER
MC68HC05JB4
9-6
REV 2
The result obtained by an input capture will be one count higher than the value of
the free-running timer counter preceding the external transition. This delay is
required for internal synchronization. Resolution is affected by the prescaler,
allowing the free-running timer counter to increment once every four internal clock
cycles (eight oscillator clock cycles).
Reading the ICRH inhibits further captures until the ICRL is also read. Reading
the ICRL after reading the timer status register (TSR) clears the ICF ag bit. does
not inhibit transfer of the free-running counter. There is no conict between read-
ing the ICRL and transfers from the free-running timer counters. The input capture
registers always contain the free-running timer counter value which corresponds
to the most recent input capture.
NOTE
To prevent interrupts from occurring between readings of the ICRH and ICRL, set
the I bit in the condition code register (CCR) before reading ICRH and clear the I
bit after reading ICRL.
9.4
OUTPUT COMPARE REGISTERS
The Output Compare function is a means of generating an interrupt when the 16-
bit timer counter reaches a selected value as shown in Figure 9-8. Software
writes the selected value into the output compare registers. On every fourth inter-
nal clock cycle (every eight oscillator clock cycle) the output compare circuitry
compares the value of the free-running timer counter to the value written in the
output compare registers. When a match occurs, the output compare interrupt
ag, OCF is set. A timer interrupt request to the CPU is generated if the output
compare interrupt enable is set, i.e. OCIE=1.
Software can use the output compare register to measure time periods, to gener-
ate timing delays, or to generate a pulse of specic duration or a pulse train of
specic frequency and duty cycle.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ICRH
R
ICRH7
ICRH6
ICRH5
ICRH4
ICRH3
ICRH2
ICRH1
ICRH0
$0014
W
reset:
UUUUUUUU
ICRL
R
ICRL7
ICRL6
ICRL5
ICRL4
ICRL3
ICRL2
ICRL1
ICRL0
$0015
W
reset:
UUUUUUUU
U = UNAFFECTED BY RESET
Figure 9-7. Input Capture Registers (ICRH, ICRL)
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