參數(shù)資料
型號： MC68HC05JB4DWR2
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PDSO28
封裝： SOIC-28
文件頁數(shù)： 106/134頁
文件大小： 1305K
代理商： MC68HC05JB4DWR2
February 24, 1999
GENERAL RELEASE SPECIFICATION
MC68HC05JB4
UNIVERSAL SERIAL BUS MODULE
MOTOROLA
REV 2
10-7
Figure 10-7. CRC Block Diagram for Data Packets
10.2.1.6 End Of Packet (EOP)
The single-ended 0 (SE0) state is used to signal an end of packet (EOP). The
single-ended 0 state is indicated by both D+ and D– being below 0.8 V. EOP will
be signaled by driving D+ and D– to the single-ended 0 state for two bit times
followed by driving the lines to the idle state for one bit time. The transition from
the single-ended 0 to the idle state denes the end of the packet. The idle state is
asserted for one bit time and then both the D+ and D– output drivers are placed in
their high-impedance state. The bus termination resistors hold the bus in the idle
state. Figure 10-8 shows the data signaling and voltage levels for an end of
packet transaction.
MUX
0
16
1
0
next bit
Input / Output
- Update every bit time
- Reset to ones at SOP
Equal?
Good CRC
Bad CRC
16
Y
N
Expected Residual:
Generator Polynomial:
Data Stream
Output
Data Stream
CRC16 Transmitted
MSB first after final
data byte.
TRANSMIT
RECEIVE
00 0 0 0
10 0 0 0
00 0 1 0 1
00 0 0 0
1 0 000
0 0 110 1
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