- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371016 > MC145572 (Motorola, Inc.) ISDN U-Interface Transceiver(ISDN U接口收發(fā)器) PDF資料下載
參數(shù)資料
| 型號(hào)： | MC145572 |
| 廠商： | Motorola, Inc. |
| 英文描述： | ISDN U-Interface Transceiver(ISDN U接口收發(fā)器) |
| 中文描述： | 綜合業(yè)務(wù)數(shù)字網(wǎng)U型接口收發(fā)器（綜合業(yè)務(wù)數(shù)字網(wǎng)ü接口收發(fā)器） |
| 文件頁(yè)數(shù)： | 123/264頁(yè) |
| 文件大?。?/td> | 2832K |
| 代理商： | MC145572 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)當(dāng)前第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)第242頁(yè)第243頁(yè)第244頁(yè)第245頁(yè)第246頁(yè)第247頁(yè)第248頁(yè)第249頁(yè)第250頁(yè)第251頁(yè)第252頁(yè)第253頁(yè)第254頁(yè)第255頁(yè)第256頁(yè)第257頁(yè)第258頁(yè)第259頁(yè)第260頁(yè)第261頁(yè)第262頁(yè)第263頁(yè)第264頁(yè)
MC145572
7–7
MOTOROLA
The
crc
Corrupt mode bit, OR9(b2), modifies the operation of
crc
Corrupt, BR8(b3). When OR9(b2)
is a 1, the operation of the
crc
Corrupt bit, BR8(b3), is modified so that a corrupt
crc
is transmitted
only to the end of the current U–interface superframe. Then BR8(b3) is cleared to a 0. If it is desired
to corrupt the transmitted
crc
again, then BR8(3) must be set to a 1 again. This is very useful for
digital loop carrier applications, since software does not have to clear BR8(b3) in order to guarantee
a one–to–one correspondence between
crc
received from the digital loop carrier system and
crc
s
transmitted onto the U–interface. For digital loop carrier applications, BR9(b1) is set to a 1 if it is
desired to have end–to–end performance monitoring. The outgoing
febe
should be updated at the
same time that the outgoing M4 channel register is updated. This update should be done for every
superframe.
This section provides details on when interrupts are generated and when the internal Superframe
Framer reads maintenance channel registers to include their contents in the outgoing transmitted
superframe. This information is particularly useful when designing LUNT and LULT line cards for digital
loop carrier systems. The basic frames and Quat positions are numbered as in the ANSI T1.601 specifi-
cation. A Quat is the ANSI T1.601 term for the symbols transmitted over the U–interface. Basic frames
are numbered from 1 through 8. The Quats in each basic frame are numbered from 1 through 120.
The M4, M5/M6, and eoc maintenance subchannels can be used for signalling in proprietary applica-
tions. When the M4 or M5/M6 subchannels are configured to update on every received frame in the
subchannel, the update interval is 12 ms or once every superframe. The receive data interrupt for
the M5/M6 subchannel occurs at the end of basic frame 4. The receive data interrupt for the M4 channel
occurs at the end of the superframe or basic frame 8. See Figures 7–1, 7–2 and 7–3, and register
BR9 description for more details.
When the eoc subchannel is configured to update on every received eoc frame, the update interval
is 6 ms, or twice each superframe. The eoc receive data interrupt can occur at the end of basic frame
4 or at the end of basic frame 8. See register description for BR9 for more details.
The receive and transmit registers for the maintenance channels are double buffered. Figure 7–2 indi-
cates where maintenance channel registers are updated from the superframe received at NT. Fig-
ure 7–2 also indicates the points where the U–interface transceiver transfers data from the mainte-
nance channel registers into the transmitted superframe when the MC145572 is configured for NT
mode. Figure 7–3 indicates where maintenance channel registers are updated from the superframe
received at the LT end of the loop. Figure 7–3 also indicates the points where the U–interface transceiv-
er transfers data from the maintenance channel registers into the transmitted superframe when the
MC145572 is configured for LT mode.
For digital loop carrier applications, maintenance channel registers R6, BR1, and BR3 must be pro-
grammed to update on every received frame. Do not use trinal or dual consecutive checking. The
reason for this, is intermediate nodes need to do local processing of the eoc messages and must
transmit the messages upstream or downstream on a frame–by–frame basis. See explanations for
Byte register 9. Note that the eoc maintenance subchannel R6 is updated with a new received eoc
message twice each superframe. The MC145572 should be configured so that interrupts are generated
when BR1, BR3, and R6 are updated. See explanations for Nibble registers 3 and 4. The interrupt
for BR3 (IRQ0) may not need to be enabled, since BR3 is updated at the same time as R6 at the
end of a superframe. When an interrupt occurs, data can be read from the appropriate maintenance
channel register (BR1, BR3, or R6) and transmitted over the digital loop carrier system. At this time,
the maintenance channel data that has been received from the digital loop carrier system can be written
to the registers for the outgoing superframe (BR0, BR2, or R6).
If the M4 channel and eoc interrupts are enabled to occur on the reception of every frame, it is possible
for the software to determine if eoc interrupt has occurred at the end of basic frame 4 or at the end
of basic frame 8. When eoc interrupt occurs at the end of basic frame 4, eoc interrupt status bit,
NR3(b2), is set and M4 channel interrupt status bit, NR3(b1), is clear assuming that M4 channel regis-
ter, BR1, was read immediately following the previous M4 channel interrupt. When eoc interrupt and
M4 interrupts occur at the end of basic frame 8, both NR3(b2) and NR3(b1) are set.
The MC145572 does not provide any direct mechanism whereby an external microcontroller can
determine when registers, for outgoing maintenance data, can be updated. This timing must be
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC145576 | ISDN NT1(ISDN 網(wǎng)絡(luò)終端) |
| MC14557BCL | 1-to-64 Bit Variable Length Shift Register |
| MC14557BFEL | 1-to-64 Bit Variable Length Shift Register |
| MC14557BDWR2 | RJZ Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 09V; Output Voltage (Vdc): 12V; Power: 2W; 2W Single and Dual Outputs in DIP 14; 3kVDC and 4kVDC Isolation; Optional Continuous Short Circuit Protected; Custom Solutions Available; UL94V-0 Package Material; Efficiency up to 85% |
| MC14557 | 1-to-64 Bit Variable Length Shift Register |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC145572AAC | 功能描述:IC TRANSCEIVER ISDN 44-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| MC145572ACR2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Freescale Semiconductor 功能描述: |
| MC145572AEI | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Freescale Semiconductor 功能描述: |
| MC145572AFN | 功能描述:IC TRANSCEIVER ISDN 44-PLCC RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| MC145572APB | 功能描述:IC ISDN INTERFACE TXCVER 44-LQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。