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參數(shù)資料
| 型號(hào)： | MB86965A |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP16 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 76/76頁 |
| 文件大?。?/td> | 394K |
| 代理商： | MB86965A |
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MB86965
9
BUFFER MEMORY INTERFACE PINS
PIN NO.
SYMBOL
MODE
TYPE
DESCRIPTION
66–79,
82–83
BD<15:2>,
BD<1:0>
0, 1, 2, 3
I/O
BUFFER MEMORY DATA BUS: Data lines between SRAM buffer
memory and EtherCoupler. This data bus configurable for 8-bit or
16-bit data size by BB/BW bit DLCR6<4>.
84–89,
93–98,
100-103
BA<15:10>
BA<9:4>
BA<3:0>
0, 1, 2, 3
O
BUFFER MEMORY ADDRESS BUS: These lines address up to
64 kbytes of buffer memory.
104
BCS1
0, 1, 2, 3
O
BUFFER RAM CHIP SELECT 1: Active low signal that is chip
select for most significant byte of buffer memory.
105
BCS0
0, 1, 2, 3
O
BUFFER RAM CHIP SELECT 0: Active low signal that is chip
select for least significant byte of buffer memory.
106
BWE
0, 1, 2, 3
O
BUFFER WRITE ENABLE: Active low, write-enable-to-buffer
-memory signal output during memory write cycles.
107
BOE
0, 1, 2, 3
O
BUFFER OUTPUT ENABLE: Active low, output-enable-to-buffer
memory signal output during memory read cycles.
POWER AND TRANSCEIVER INTERFACE PINS
PIN NO.
SYMBOL
MODE
TYPE
1, 19, 31, 32,
52, 53, 62, 81,
116, 121
VCC
0, 1, 2, 3
I
POWER SUPPLY: +5 Volts
± 5%, for analog and digital circuits.
16, 20, 29, 30,
37, 56, 61, 65,
80, 99, 120,
140, 160
GND
0, 1, 2, 3
I
GROUND: digital and analog ground.
45, 46
48, 49
DOP
DON
0, 1, 2, 3
O
AUI TRANSMIT PAIR: Differential output driver pair for AUI
transceiver DO circuits; output is Manchester-encoded.
42
43
DIP
DIN
0, 1, 2, 3
I
AUI RECEIVE PAIR: A differential input driver pair for the AUI
transceiver DI circuits; input is Manchester-encoded.
54
55
CIP
CIN
0, 1, 2, 3
I
AUI COLLISION PAIR: A differential input driver pair for the AUI
transceiver CI circuits.
The input is collision signalling or
signal-quality error (SQE).
28, 34
25, 36
TPOPA,TPONA
TPOBP,TPONB
O
TWISTED-PAIR OUTPUT: Differential driver pair outputs to the
twisted-pair cable. The output is pre-equalized so that no external
filter is required.
38,
39
TPIP
TPIN
0, 1, 2, 3
I
TWISTED-PAIR INPUT: A differential input pair from the
twisted-pair cable.
60
LEDC
0, 1, 2, 3
O
COLLISION LED: Open-drain driver for the collision indicator.
Output is pulled low during collision.
60
LEDC / FDX
0, 1, 2, 3
O/I
MB86965B only: FULL DUPLEX: When tied low, the 10 BASE–T
port will operate in full–duplex mode. It does this by disabling the
collision function of the 10 BASE–T port.
59
LEDL
0, 1, 2, 3
O
LINK LED: Open-drain driver for link integrity indicator. Output is
pulled low during link test pass.
58
LEDT
0, 1, 2, 3
O
TRANSMIT LED: Open-drain driver for transmit indicator. Output
is pulled low during transmit.
57
LEDR
0, 1, 2, 3
O
RECEIVE LED: Open-drain driver for the receive indicator. Output
is pulled low during receive.
21
RBIAS
0, 1, 2, 3
I
BIAS RESISTOR: To control bias of operating circuit; pulled to
ground with 12.4-kilohm
±1% pulldown resistor.
17
18
CLKO
CLKI
0, 1, 2, 3
O
CRYSTAL OSCILLATOR: A 20-MHz crystal must be connected
between these pins. [See figure 4.]
22–24, 26, 27,
33, 35, 40, 41,
44, 47, 50, 51
No Connection
0, 1, 2, 3
O
NOT USED. These pins should be left floating, internally pulled
high.
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| MB86965B | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:EtherCoupler ETHERNET CONTROLLER WITH 10BASE?T TRANSCEIVER |
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| MB86967PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces |
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