參數(shù)資料
型號(hào)： MB86965A
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP16
封裝： PLASTIC, QFP-160
文件頁(yè)數(shù)： 40/76頁(yè)
文件大?。?/td> 394K
代理商： MB86965A
MB86965
45
System Access To Buffer
EtherCoupler supports programmed-I/O, Single-cycle
and Burst mode DMA transfers between buffer memory
and host system. The host accesses buffer memory by
reading from or writing to EtherCoupler Buffer Memory
Port register BMPR8. Data read or written by the system
passes through on-chip FIFOs to eliminate effects of
real-time interaction among the system, Transmitter and
Receiver, as each accesses buffer memory. EtherCoupler
also automatically controls read and write operations to
external static random-access memory (SRAM).
Transmitter Access To Buffer
Programming
Buffer
Size
bits
BS1
and
BS0,
DLCR6<1:0>, changes the size of each transmit bank.
Software allocates transmit buffer size as a single
2-kilobyte Transmit buffer, or as pairs of 2, 4 or
8-kilobyte Transmit buffers. A single packet or multiple
packets simultaneously load into the buffer for
transmission. The system and Transmitter time-share the
buffer with a single Transmit buffer. The system utilizes
two Transmit buffer sections to load packets into one of
the buffers, while contents of the other buffer section are
transmitted.
At reset, pointers initialize to set a beginning for one of
the Transmit buffers. Each time the host writes data to the
buffer via the Buffer Memory Port register, an internal
pointer advances to the next memory location within the
Transmit buffer. Once a data byte/word is written, it
cannot be read and the internal pointer cannot be
reversed.
EtherCoupler manages internal pointers that control
access by the host to the two banks and selection of
specific bank bytes and words. EtherCoupler switches
banks as soon as TX START bit, BMPR10<7>, is set high
by the host system, after which EtherCoupler begins
transmitting at the earliest opportunity. The Transmit-
Read pointer, which is also automatically managed,
sequences through the transmitted bank to read packet
data into the Transmitter through its FIFO. If a collision
occurs, the packet automatically retransmit after a
pseudo-random (backoff interval) waiting period.
EtherCoupler continues down the list, automatically
transmitting all multiple packets in the bank. EtherCoup-
ler can transmit multiple, back-to-back packets of legal
Ethernet sizes to the LAN network. Excluding preamble
and CRC fields, these packets can be between 60 and
1514 bytes.
Figure 13. Transmit Buffer Detail
As shown in Figure 13, multiple packets can reside within
one transmit bank, separated by a nontransmitted,
two-byte header that provides packet byte-length
information. At the end of a packet list or chain, the
Transmitter stops, updates its status bits and, if enabled,
generates an interrupt.
Transmit Packet Data Formats
Packets to be transmitted (minus preamble and CRC
fields) first load into the Transmit buffer with a two-byte
header indicating packet byte-length. If buffer space
permits, multiple packets load simultaneously. After
packet-loading, the host initiates transmission by writing
the number of packets just loaded into TX PKT CNT bits,
BMPR10<6:0>. If the two-bank buffer configuration is
selected, the second bank now loads additional packets.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MB86965B 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:EtherCoupler ETHERNET CONTROLLER WITH 10BASE?T TRANSCEIVER
MB86965BPF-G-BND 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:EtherCoupler ETHERNET CONTROLLER WITH 10BASE?T TRANSCEIVER
MB86967 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces
MB86967PFV 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces
MB86977 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IP PACKET FORWARDING ENGINE
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