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參數(shù)資料
| 型號： | MB86965A |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP16 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 29/76頁 |
| 文件大?。?/td> | 394K |
| 代理商： | MB86965A |
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MB86965
35
Figure 9 shows the Cyclical Redundancy Check (CRC)
register core, which is a modified shift-right register used
to generate and check CRCs. While some controllers
share a single core between transmitter and receiver,
EtherCoupler has one core for the generator and one core
for the checker, thus allowing concurrent operation
during self-receive.
To begin the calculation, the register is first set to all ones.
For the generator case, as the packet transmits, data is
clocked serially into the left-hand end of the register,
starting with 48 bits of the destination address (the
Preamble is skipped). After the last bit of the data field
clocks into the register, the CRC calculation finishes. The
feedback line is then forced low by the NOR gate, and the
register becomes a simple shift-right register. Its contents
then shift out serially, and are transmitted while
appending the CRC to the end of the packet. Calculation
for the CRC checker begins similar to CRC generation,
by feeding the incoming data into the register. But the
CRC field of the packet also feeds the calculation. The
result is a fixed constant in the register, if no CRC error
occurs.
For the Hash Filter, after the last bit of the destination
address clocks into the register, the left-hand six register
bits store in another register used to address the Hash
Table elements. The left-most bit is most significant. The
left-most three bits are used as the Hash Table register
address, and the right-most three bits are used as the bit
address within a register byte. Such selection of a Hash
Table element yields a 1 in the table to indicate that the
packet will be accepted, if it is a multicast packet (first bit
of destination address equals 1), and passes the error
filters.
The hash filter is used only when the Address Filter mode
select bit AF1 is 1 and mode select bit AF0 is 0, selecting
the Node ID, Broadcast, Multicast + Hash Table mode.
Like the Node ID registers, Hash Table registers should
only be accessed when the Receiver is disabled, i.e., when
DLC EN is high, to avoid interaction with the Receiver.
(Software code examples showing how to calculate
entries for the Hash Table are available through the
Fujitsu Customer Response Center 1–800–866–8608.
There are eight bytes of registers in the Hash Table
containing 64 one-bit elements, as shown in the Control
and Status Table 11.
TRANSMIT AND RECEIVE PACKET HEADERS
Buffer memory is partitioned into Transmit and Receive
sections, which store Packet Headers that precede
associated outgoing and incoming packet information.
The Transmit Packet Header stored in the first two bytes
of the Transmit Buffer reflects length characteristics of
the current outgoing packet. Subsequent Transmit Buffer
bytes store the contents of Destination ID, Source ID,
Length, and Data fields of the outgoing packet.
The Receive Packet Header stored in the first four bytes of
the Receive Buffer reflects packet conditions and length
characteristics of the current incoming packet. (Refer to
the discussion of Receive Status register DLCR1 for
received errors.) Subsequent Receive Buffer bytes store
the contents of Destination ID, Source ID, Length, and
Data fields of the incoming packet.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB86965B | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:EtherCoupler ETHERNET CONTROLLER WITH 10BASE?T TRANSCEIVER |
| MB86965BPF-G-BND | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:EtherCoupler ETHERNET CONTROLLER WITH 10BASE?T TRANSCEIVER |
| MB86967 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces |
| MB86967PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces |
| MB86977 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IP PACKET FORWARDING ENGINE |
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