參數資料
型號: MB86965A
元件分類: 微控制器/微處理器
英文描述: 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP16
封裝: PLASTIC, QFP-160
文件頁數: 62/76頁
文件大?。?/td> 394K
代理商: MB86965A
MB86965
65
Table 45. Single-cycle DMA Timing
SYMBOL
PARAMETER DESCRIPTION
MINIMUM
MAXIMUM
UNITS
t1
DMACK low to DREQ low
0
21
ns
t2
DMACK high to DREQ high
0
19
ns
t3
DMACK low to IOR or IOW low
0
ns
t4
IOR or IOW high to DMACK high
3
ns
t5
IOR or IOW low to EOP low
0
ns
t6
EOP high to DMACK high
3
ns
t7
EOP low pulse width
19
ns
All of the IOR, IOW and EOP low-going pulses must fall inside of the DMACK low-going pulse. An asserted EOP terminates
any further DREQ after DMACK returns high. The DMA cycle uses DMACK as the chip select. DMACK overrides SA<3:0>,
forcing selection of the Buffer Memory Port as in a DMA cycle.
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