參數(shù)資料
型號: MB86965A
元件分類: 微控制器/微處理器
英文描述: 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP16
封裝: PLASTIC, QFP-160
文件頁數(shù): 63/76頁
文件大小: 394K
代理商: MB86965A
MB86965
66
Table 46. Burst DMA Timing
SYMBOL
PARAMETER DESCRIPTION
MINIMUM
MAXIMUM
UNITS
t1
IOR or IOW low to DREQ low
32
ns
t2
IOR or IOW high to DACK high
3
ns
t3
IOR or IOW low to DREQ low, if DREQ EXTND (DLCR4<2>) is
set to 1 (default)
32
ns
All of the IOR, IOW and EOP low-going pulses must fall inside of the DMACK low-going pulse. The DMA cycle uses DMACK as
the chip select. DMACK overrides SA<3:0>, forcing selection of the Buffer Memory Port as in a DMA cycle. DREQ goes low
during the next-to-last transfer of the burst, and can be extended from the next-to-last transfer cycle when DREQ EXTND,
DLCR4<2>, is low to the last transfer cycle when DREQ EXTND is high.
Burst can be interrupted by DMACK high-going pulse during the burst. Burst will resume when DMACK returns low. DREQ
goes low during the nest-to-last transfer of the burst.
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