參數(shù)資料
型號(hào)： MB86965A
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP16
封裝： PLASTIC, QFP-160
文件頁(yè)數(shù)： 17/76頁(yè)
文件大小： 394K
代理商： MB86965A
MB86965
24
Receive Status Register
Table 13. DLCR1 — Receive Status Register
BIT
SYMBOL
TYPE
DESCRIPTION
7
RX PKT
RC0
RECEIVE PACKET: Set when a new receive packet is stored on the Receive
Buffer. Can generate interrupts if enabled by INT EN bit, DCLR3<7>.
6
BUS TS
ERR
RC0
BUS READ ERROR: Set when a ready response cannot be issued within 2.4
milliseconds after the SMEMRD signal is asserted. Occurs when reading an
empty buffer. Can generate interrupts if enabled by INT EN bit, DCLR3<6>.
5
DMA EOP
RC0
DMA END OF PROCESS: Set when the host DMA asserts the EOP pin
indicating that the process is finished. when set, inhibits further assertion of
DREQ. Cleared by writing 00H to BMPR12, or by writing 1 to this bit. Can
generate interrupts if enabled by INT EN bit, DCLR3<5>.
4
RMT
09900H
RC0
REMOTE CONTROL PACKET RECEIVED: This bit is set if a packet is
received with 0900H in its Length/Type field (two bytes following the source
address, received MSB first). Can generate interrupts if enabled by INT EN
bit, DCLR3<4>.
3
SHORT PKT
ERR
RC0
SHORT PACKET ERROR: This bit is set when a packet is received with less
than 60 bytes, excluding its Preamble and CRC fields. Such a packet usually
indicates a collision has truncated its original length, since IEEE 802.3
minimum length is 60 bytes. Can generate interrupts if enabled by INT EN bit,
DCLR2<3>.
2
ALIGN
ERR
RC0
ALIGNMENT PACK ERROR: This bit will assert if a packet is received with
an alignment error, meaning there were 1 to 7 extra bits at the end of the
packet. Such an occurrence usually indicates a collision, or a faulty
transceiver. Can generates interrupts if enabled by INT EN bit, DCLR3<2>.
1
CRC
ERR
RC0
CRC PACK ERROR: This bit is set if a packet is received with a CRC error.
This usually indicates a collision has corrupted the packet. Can generate
interrupts if enabled by INT EN bit, DLCR3<1>.
0
RX BUR
OVEFLO
RC0
RECEIVE BUFFER OVERFLOW: This bit will be set if the Receive Buffer
becomes full and must reject a packet for lack of space. Can generate
interrupts if enabled by INT EN bit, DLCR3<0>.
As shown in Table 13, this register contains eight status
bits which can generate interrupts if enabled by the
corresponding bit in DLCR3. Five of these bits report the
status of the most recently received packet accepted for
storage in the Receive Buffer. Bit 7, RX PKT, is set
whenever a new packet is successfully received and
stored in the buffer. One bit reports reception of a special
packet with 0900H in its type field. Other bits in this
register report buffer overflow, DMA end of process, and
bus read error. Bits 1, 2 and 3 indicate errors, if any,
detected in the packet. If ACPT BAD PKTS bit,
DLCR5<5> or ACPT SHORT PKTS bit, DLCR5<3>
are set allowing acceptance of a bad packet, these error
indicators will be stored in the Status Byte of the Receive
Packet Header. If DLCR5<5> and/or DLCR5<3> are
both 0, all packets with detected errors are automatically
discarded and not stored in the buffer.
The bits in this register are cleared by writing 1 to the bit.
Writing 0 to these bits has no effect; only EtherCoupler
control logic can set these bits. Clearing the bit that causes
an interrupt clears the bit and the interrupt. Because two or
more status conditions can occur simultaneously, the
interrupt routine must read and act on all status conditions
that are set. One method to clear interrupts is to read the
contents of the status register, then write the same value
back to the register, thus clearing all bits that were set.
Another technique is to clear each status bit separately, by
writing its (interrupt enable) mask to the register. This
might be done as the corresponding interrupt service is
performed. Note that wholesale clearing of all status bits
by writing FFH to the register is not recommended,
because this action may clear a just-set status that has not
yet been read by the system.
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