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參數(shù)資料
| 型號： | MB86965A |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP16 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 5/76頁 |
| 文件大?。?/td> | 394K |
| 代理商： | MB86965A |
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MB86965
13
negates WE. In burst mode and depending on CNTRL
bit, DLCR4<2>, at the next-to-last cycle, EtherCoupler
negates DREQ. The host DMA then completes the last
two transfer cycles and negates DACK to close the burst.
To start another burst, EtherCoupler re-asserts DREQ.
The number of DMA write cycles within one burst can be
1, 4, 8, or 12 data transfers (bytes or words), depending
on burst control bits BURST 1 and BURST 0,
BMPR13<1:0>.
The DMA controller asserts the end of process input,
EOP, concurrent with the last data-transfer cycle to
indicate completion of the entire transfer process. This
action sets the DMA EOP bit, DLCR1<5>, to
discontinue further EtherCoupler data requests. Setting
the EOP signal will also generate an interrupt. If the
DMA EOP INT enable bit, DLCR3<5>, is high. the host
can use this interrupt to begin action to close the process.
The host should reset EtherCoupler’s DMA logic and
clear the interrupt by resetting the DMA enable bit,
BMPR12<0>.
The transmit DMA process must be closed by clearing
BMPR12<0> before attempting another DMA process.
Clearing the DMA EOP INT EN bit, BMPR3<5>, then
automatically clears the EOP status and interrupt,
removing the need to clear the interrupt separately. The
host initiates packet transmission after loading packets
into the buffer by loading the number of packets to be
transmitted into the TX PKT CNT bits, BMPR10<6:0>,
and asserting TX START bit, BMPR10<7>.
DMA Read (Receive)
EtherCoupler indicates when it receives packets to be
read with status bits or interrupts. Before reading a packet,
the host processor can read the RX BUF EMPTY bit,
DLCR5<6>, which if 0 indicates one or more packets in
the receive buffer to read. After reading each packet, the
host again checks this bit for more packets.
Before transferring a packet via DMA from the receive
buffer to host memory, the host first reads the buffer
four-byte receive packet header to obtain packet status
and packet byte length. [Also refer to the discussion of
Transmit and Receive Packet Headers.] The host
calculates and loads the host DMA controller cycle
counter with the number of DMA cycles needed to read
the packet. The system memory starting address must
also be loaded into the DMA controller. The RX DMA
EN bit, BMPR12<1>, is next set to enable the DMA read
operation and transfer the packet to host memory. When
ready to begin this transfer, EtherCoupler sets the DMA
request output DREQ, and the host responds by asserting
DMA acknowledge bit, DMACK, and then I/O Read,
IOR. EtherCoupler sets the IOCHRDY output when the
byte/word is on the data bus, and the data transfer cycle is
ready to be completed. After system memory accepts the
data, the host negates IOR. EtherCoupler then “pops” the
data in the Bus Read FIFO, and points the internal Bus
Read pointer to the next buffer byte/word to move that
data into the FIFO.
If programmed for burst operation and depending on
CNTRL bit, DLCR4<2>, EtherCoupler negates DREQ
two cycles before the end of the burst, then re-asserts
DREQ to repeat the process, if it can transfer more data
after the host negates DMACK. The number of DMA
read cycles in a burst can be 1, 4, 8, or 12 data-transfer
(byte or word) cycles, depending on burst control bits
BURST1 and BURST0, BMPR13<1:0>. The DMA
controller asserts the end of process input EOP
concurrent with the last byte/word data transfer to
indicate completion of the entire process. EtherCoupler
then stops requesting more DMA cycles. After the DMA
process, RX DMA enable must be cleared then
re-asserted when the host wants to begin reading another
packet from the Receive Buffer by using DMA.
When the host DMA controller asserts EOP, the DMA
EOP bit, DLCR1<5>, is set and generates an interrupt, if
so enabled by setting the associated INT EN bit,
DLCR3<5>. The host can use this interrupt to close the
receive DMA process. Writing 000H to the DMA EN
bits, BMPR12<1:0>, clears the interrupt and disables and
resets the DMA, removing the need to clear the interrupt
separately. The receive DMA process must be terminated
before attempting another DMA process.
ETHERCOUPLER INTERFACE TO AT BUS
As shown in Figure 7, EtherCoupler provides jumpered
(with ID PROM or serial ID EEPROM) and jumperless
design
solutions. Designed primarily for AT Bus
Systems, EtherCoupler assumes that the program I/O
mode is the most effective way to transfer data between
controller and system resources.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB86965B | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:EtherCoupler ETHERNET CONTROLLER WITH 10BASE?T TRANSCEIVER |
| MB86965BPF-G-BND | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:EtherCoupler ETHERNET CONTROLLER WITH 10BASE?T TRANSCEIVER |
| MB86967 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces |
| MB86967PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces |
| MB86977 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IP PACKET FORWARDING ENGINE |
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