
MB86965
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RECEIVE PACKET PROCESSING
Figure 17. 8802-3 Packet Format
Figure 17 illustrates the 8802-3 packet format. When a
received packet enters from the network, its destination
address field is tested for address filter criteria selected by
the Hash Table and Address Filter Mode bits AF1 and
AF0, DLCR5<1:0>. If the address meets filter criteria, the
Receive Buffer accepts the packet for storage. The packet
must also be error-free unless the reception of flawed
packets is allowed, e.g., for diagnostic purposes. If
conditions are met, packet reception results in the Buffer
storing the packet, updating the four-byte header at the
end of reception, clearing the RX BUF EMPTY bit,
setting the RX PKT bit high, and (if enabled) generating
an interrupt. Otherwise the packet is discarded, and
pointers reset to reuse the same portion of memory for the
next arriving packet. A flawed packet accepted for
storage for diagnostic purposes is reported as an error in
the PKT STATUS byte of its header. The Receive Packet
Header bit positions for PKT STATUS are shown in
Table 24, Receive Packet Header Conditions.
NETWORK MANAGEMENT
Error, traffic and performance statistics may be collected
continuously or on a sampled basis. The Receive Status
register and Transmit Status register indicate detected
errors. Such data can be collected in two ways: interrupts
can be used after each packet, and the interrupt service
routine reads the status from the status register; or packets
are accepted for storage in the Receive Buffer in Accept
Bad Packets mode, and content and error status stored in
the header are
later read in batch mode. Frequent
selection of the Accept all packets mode to get maximum
statistics for the network and to count all packets
including their length, because it maximizes host
overhead with user terminal equipment, is discouraged.
Sampling of carrier detection estimates network
bandwidth utilization, via Transmit Status register NET
BSY bit, DLCR0<6>. Average media-access waiting
time is estimated by calculating the elapsed time between
starting the Transmitter and TX DONE bit, DLCR0<7>,
going high, and subtracting calculated transmit time.
Collision counter bits COL CTR3 through COL CTR0,
DLCR4<7:4>, determine the number of collisions
encountered by the last outgoing packet. The counter
resets at the start of transmission of each packet.
RECEIVE ERROR PROCESSING
Interrupts may optionally be generated by these receive
error conditions: buffer overflow, CRC error, alignment
error, and short packet. None of these errors requires
special host processing or intervention, other than
optional tallying of the error for network management
purposes. EtherCoupler automatically discards any
packet with errors. If a buffer overflow occurs,
EtherCoupler automatically handles that as well. Packets
already stored in the buffer are not lost. The host simply
reads out some of the packet data, freeing space in the
buffer for more packets. EtherCoupler then automatically
resumes reception of packets, as long as there is buffer
space. To prevent packet loss although EtherCoupler
automatically recovers, avoid overflow by rapidly
processing incoming packets.