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參數(shù)資料
| 型號： | MB86965A |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP16 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 18/76頁 |
| 文件大?。?/td> | 394K |
| 代理商： | MB86965A |
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MB86965
25
Transmit Interrupt Enable Register
Table 14. DLCR2 — Transmit Interrupt Enable Register
BIT
SYMBOL
TYPE
DESCRIPTION
7
INT EN
RC0
INTERRUPT ENABLE: When high, enables TX DONE to generate interrupt.
Also DCLR0<7>.
6
0
N0
RESERVED: Write 0.
5
0
N0
RESERVED: Write 0.
4
0
N0
RESERVED: Write 0.
3
INT EN
RC0
INTERRUPT ENABLE: When high, enables JABBER to generate interrupt.
Also DCLR0<3>.
2
INT EN
RC0
INTERRUPT ENABLE: When high, enables COL to generate interrupt. Also
DCLR0<2>.
1
16 COL
INT EN
RC0
INTERRUPT ENABLE: When high, enables 16 COL to generate interrupt.
Also DCLR0<1>.
0
N0
RESERVED: Write 0.
Receive Interrupt Enable Register
Table 15. DLCR3 — Receive Interrupt Enable Register
BIT
SYMBOL
TYPE
DESCRIPTION
7
INT EN
RC0
INTERRUPT ENABLE: When high, enables RX PKT to generate interrupt.
Also DCLR1<7>.
6
INT EN
RC0
INTERRUPT ENABLE: When high, enables BUS RS ERR to generate
interrupt. Also DCLR1<6>.
5
INT EN
RC0
INTERRUPT ENABLE: When high, enables DMA EOP to generate interrupt.
Also DCLR1<5>.
4
INT EN
RC0
INTERRUPT ENABLE: When high, enables RMT 0900H to generate
interrupt. Also DCLR1<4>.
3
INT EN
RC0
INTERRUPT ENABLE: When high, enables SHORT PKT ERR to generate
interrupt. Also DCLR1<3>.
2
INT EN
RC0
INTERRUPT ENABLE: When high, enables ALIGN ERR to generate
interrupt. Also DCLR1<2>.
1
INT EN
RC0
INTERRUPT ENABLE: When high, enables CRC ERR to generate interrupt.
Also DCLR1<1>.
0
INT EN
RC0
INTERRUPT ENABLE: When high, enables RX BUF OVERFLO to generate
interrupt. Also DCLR1<0>.
As shown in Table 14, this register contains the bits that
enable the status bits in DLCR0 to generate interrupts. Bit
4 extends the DMA Request from the next-to-last to the
last transfer cycle. Only bits 7, 3, 2, and 1 can generate
interrupts; the other interrupt enable bits are not used.
As shown in Table 15, this register provides control for
enabling interrupts based on the setting of status bits in
DLCR1, the Receive Status register.
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