參數(shù)資料
型號(hào)： MB86965A
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP16
封裝： PLASTIC, QFP-160
文件頁(yè)數(shù)： 2/76頁(yè)
文件大?。?/td> 394K
代理商： MB86965A
MB86965
10
SYSTEM CONFIGURATION
Figure 4. System Configuration
Simplified Block Diagram
As shown in Figure 4, EtherCoupler allows a highly
integrated system configuration. EtherCoupler’s archi-
tecture and high level of integration facilitate packet
management and storage, and eliminate the need for a
local microprocessor. EtherCoupler connects with the
host system bus to provide command and status interfaces
as well as packet data access. The host processor can
directly access command and status registers when
mapped into the host I/O or memory space. Data packets
to be transmitted to the media initially transfer from host
memory through an EtherCoupler port into a dedicated
buffer memory where they are temporarily stored until
transmitted. Buffer memory initially stores received data
packets that are later transferred to the host memory.
[Refer to the section on Control and Status Registers for
identification of control and status bits of the data link
control registers, DLCR0 through DLCR7, and buffer
memory port register pair, BMPR8 and BMPR9.]
CONNECTION TO THE LAN MEDIA
Connection to the LAN media can be accomplished by
on-board connection to a shielded or unshielded twisted
pair, through the on-chip 10BASE-T transceiver.
CRYSTAL OSCILLATOR
The clock rate of 10 Mbits/s specified by the international
LAN standard, ISO/ANSI/IEEE 8802-3, derives from an
on-chip oscillator that is controlled by a crystal connected
across pins 17 and 18 (CLKO and CLKI). Capacitance
specified by the crystal manufacturer must
EtherCoupler
CLKO
CLKI
20 MHz
20 pF
Figure 5. Crystal Oscillator Connection
be connected across pins 17 and 18 to ground, as shown
in Figure 5, to stabilize the effects of stray capacitance that
may vary crystal frequency. The 20-MHz clock also
serves as an internal phase-locked loop (PLL) reference
for decoder clock recovery. Internal clocks shut down
when the PWRDN bit, DLCR7<5>, is asserted for power
down mode. Use a crystal with the following
specifications: quartz (AT-cut); 20-MHz; frequency/ac-
curacy of
± 50ppm at 25_C and 100ppm at 0_C to 70_C;
parallel resonant with 20 pF-load in fundamental mode.
Possible vendors include: Ecliptek Corp. (Costa Mesa,
CA) p/n ECSM20.000M; and M-tron Industries, Inc.
(Yankton, SD) p/n MP-1 and MP-2, with 20-MHz,
50ppm over 0
_C to 70_C, and 18 pF fundamental load.
SRAM CONFIGURATIONS
Figure 6 shows how to configure industry-standard
SRAMs for memory implementation of packet buffers in
byte and word modes. The Buffer Byte/Buffer Word
(BB/BW) bit, DLCR6<4>, selects the width of the
SRAM data path as 8 or 16 bits. Setting this bit to 1 selects
byte-wide (8-bit) data; setting it to 0 selects word-wide
(16-bit) data. The System Byte/System Word (SB/SW)
bit, DLCR6<5>, selects the width of the system data path
as 8 or 16 bits. Setting this bit to 1 selects byte-wide
(8-bit) data; setting it to 0 selects word-wide (16-bit)
data. Do not use the combination of SB/SW bit,
DLCR6<5>, set to 1 (byte) and BB/BW bit, DLCR6<4>,
set to 0 (word). The Buffer Size (BS1 and BS0) bits,
DLCR6<1:0>, select SRAM size as 8, 16, 32 or
64kbytes.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MB86965B 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:EtherCoupler ETHERNET CONTROLLER WITH 10BASE?T TRANSCEIVER
MB86965BPF-G-BND 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:EtherCoupler ETHERNET CONTROLLER WITH 10BASE?T TRANSCEIVER
MB86967 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces
MB86967PFV 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces
MB86977 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IP PACKET FORWARDING ENGINE
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