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M16C/28 Group
Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
7. Clock Generation Circuit
Rev.0.60 2004.02.01
page 49 of N
REJ09B0047-0060Z
Table 7.6.1. Allowed Transition and Setting
High-speed mode,
middle-speed mode
Ring oscillator mode
Stop mode
Wait mode
Ring oscillator
low power dissipation
mode
PLL operation mode2
Low power dissipation
mode
Low-speed mode2
Current
state
State after transition
See Table A
8
--
(8)
(18)5
(9)7
--
(10)
(11)1, 6
(12)3
(14)4
--
(13)3
(15)
--
(10)
--
(18)
--
(16)1
(17)
(16)1
(17)
(16)1
(17)
(16)1
(17)
(16)1
(17)
--
(18)5
(18)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
Setting
Operation
CM04 = 0
Sub clock turned off
CM04 = 1
Sub clock oscillating
CM06 = 0,
CPU clock no division mode
CM17 = 0 , CM16 = 0
CM06 = 0,
CPU clock division by 2 mode
CM17 = 0 , CM16 = 1
CM06 = 0,
CPU clock division by 4 mode
CM17 = 1 , CM16 = 0
CM06 = 1
CPU clock division by 8 mode
CM06 = 0,
CPU clock division by 16 mode
CM17 = 1 , CM16 = 1
CM07 = 0
Main clock, PLL clock,
or ring oscillator clock selected
CM07 = 1
Sub clock selected
CM05 = 0
Main clock oscillating
CM05 = 1
Main clock turned off
PLC07 = 0,
CM11 = 0
Main clock selected
PLC07 = 1,
CM11 = 1
PLL clock selected
CM21 = 0
Main clock or PLL clock selected
CM21 = 1
Ring oscillator clock selected
CM10 = 1
Transition to stop mode
wait instruction
Transition to wait mode
Hardware interrupt
Exit stop mode or wait mode
Notes:
1. Avoid making a transition when the CM21 bit is set to “1” (oscillation stop, re-oscillation detection function enabled).
Set the CM21 bit to “0” (oscillation stop, re-oscillation detection function disabled) before transiting.
2. Ring oscillator clock oscillates and stops in low-speed mode. In this mode, the ring oscillator can be used as peripheral function clock.
Sub clock oscillates and stops in PLL operation mode. In this mode, sub clock can be used as peripheral function clock.
3. PLL operation mode can only be entered from and changed to high-speed mode.
4. Set the CM06 bit to “1” (division by 8 mode) before transiting from ring oscillator mode to high- or middle-speed mode.
5. When exiting stop mode, the CM06 bit is set to “1” (division by 8 mode).
6. If the CM05 bit is set to “1” (main clock stop), then the CM06 bit is set to “1” (division by 8 mode).
7. A transition can be made only when sub clock is oscillating.
8. State transitions within the same mode (divide-by-n values changed or subclock oscillation turned on or off) are shown in the table below.
--: Cannot transit
(11)1
High-speed mode,
middle-speed mode
Ring oscillator
mode
Stop mode
Wait mode
Ring oscillator
low power
dissipation mode
PLL operation
mode2
Low power
dissipation mode
Low-speed mode2
See Table A
8
See Table A
8
(3)
(4)
(5)
(7)
(5)
(7)
(6)
No
division
Divided
by 2
(3)
(4)
(5)
(7)
(6)
(1)
(2)
--
Sub clock oscillating
Sub clock turned off
--: Cannot transit
Divided
by 4
Divided
by 8
Divided
by 16
No
division
Divided
by 2
Divided
by 4
Divided
by 8
Divided
by 16
No division
Divided by 4
Sub
clock
oscillating
Sub
clock
turned
of
f
Divided by 8
Divided by 16
Divided by 2
No division
Divided by 4
Divided by 8
Divided by 16
Divided by 2
9. ( ) : setting method. Refer to following table.
CM04, CM05, CM06, CM07 : bit of CM0 register
CM10, CM11, CM16, CM17 : bit of CM1 register
CM20, CM21
: bit of CM2 register
PLC07
: bit of PLC0 register