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M16C/28 Group
Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
5. Reset
Rev.0.60 2004.02.01
page 26 of N
REJ09B0047-0060Z
Figure 5.5.3. VCR1 Register, VCR2 Register, and D4INT Register
VC13
Voltage detection register 1
Symbol
Address
After reset (Note 2)
VCR1
001916
000010002
Voltage down monitor flag
(Note 1)
Bit name
Function
Bit symbol
RW
b7
b
6
b
5
b4
b
3
b
2
b1
b
0
Note 1: The VC13 bit is useful when the VC27 bit of VCR2 register is set to “1” (voltage down detection circuit
enable). The VC13 bit is always “1” (VCC
≥ Vdet4) when the VC27 bit in the VCR2 register is set to “0” (voltage
down detection circuit disable).
Note 2: This register does not change at software reset, watchdog timer reset and oscillation stop detection reset.
0:VCC < Vdet4
1:VCC
≥ Vdet4
RO
0 0 0 0
0 0 0
RW
Reserved bit
Must set to “0”
Voltage detection register 2 (Note 1)
Symbol
Address
After reset (Note 6)
VCR2
001A16
0016
Bit name
Bit symbol
b7
b
6
b
5
b4
b
3
b
2
b1
b
0
Note 1: Write to this register after setting the PRC3 bit in the PRCR register to “1” (write enable).
Note 2: When not in stop mode, to use hardware reset 2, set the VC26 bit to “1” (reset level detection circuit enable).
Note 3: To use hardware reset 2 in stop mode, set the VC25 bit to “1” (RAM retention limit detection circuit enable).
VC26 bit is disabled in stop mode. (The microcomputer is not reset even if the voltage input to Vcc1 pin
becomes lower than Vdet3.)
Note 4: To use the WDC5 bit in the WDC register, set the VC25 bit to “1” (RAM retention limit detection circuit enable).
Note 5: When the VC13 bit in the VCR1 register and D42 bit in the D4INT register are used or the D40 bit is set to “1”
(voltage down detection interrupt enable), set the VC27 bit to “1” (voltage down detection circuit enable).
Note 6: This register does not change at software reset, watchdog timer reset and oscillation stop detection reset.
Note 7: The detection circuit does not start operation until td(E-A) elapses after the VC25 bit, VC26 bit, or VC27 bit are
VC25
RAM retention limit
detection monitor bit
(Notes 3, 4, 7)
0: Disable RAM retention limit
detection circuit
1: Enable RAM retention limit
detection circuit
VC26
VC27
RW
0 0 0 0 0
Function
Reserved bit
Must set to “0”
Reset level monitor bit
(Notes 2, 3, 7)
0: Disable reset level detection
circuit
1: Enable reset level detection
circuit
Voltage down monitor
bit (Note 5)
0: Disable voltage down
detection circuit
1: Enable voltage down
detection circuit
(b2-b0)
(b7-b4)
(b4-b0)
D40
Voltage down detection interrupt register (Note 1)
Symbol
Address
After reset
D4INT
001F16
0016
Voltage down detection
interrupt enable bit (Note 5)
Bit name
Bit symbol
b7
b6
b5
b4
b3
b2
b1
b0
0 :
Disable
1 :
Enable
D41
STOP mode deactivation
control bit
(Note 4)
0: Disable (do not use the voltage
down detection
interrupt to get out of stop mode)
1: Enable (use the voltage down
detection interrupt to get
out of stop mode)
D42
Voltage change detection flag
(Note 2)
0: Not detected
1: Vdet4 passing detection
D43
WDT overflow detect flag
0: Not detected
1: Detected
DF0
Sampling clock select bit
00 : CPU clock divided by 8
01 : CPU clock divided by 16
10 : CPU clock divided by 32
11 : CPU clock divided by 64
DF1
Note 1: Write to this register after setting the PRC3 bit in the PRCR register to “1” (write enable).
Note 2: Useful when the VC27 bit in the VCR2 register is set to “1” (voltage down detection circuit enabled). If the
VC27 bit is set to “0” (voltage down detection circuit disable), the D42 bit is set to “0” (Not detect).
Note 3: This bit is set to “0” by writing a “0” in a program. (Writing a “1” has no effect.)
Note 4: If the voltage down detection interrupt needs to be used to get out of stop mode again after once used for
that purpose, reset the D41 bit by writing a “0” and then a “1”.
Note 5: The D40 bit is effective when the VCR2 register VC27 bit = 1. To set the D40 bit to “1”, follow the
procedure described below.
(1) Set the VC27 bit to “1”.
(2) Wait for td(E-A) until the detection circuit is actuated.
(3) Wait for the sampling time (refer to “Table 5.5.1.2 Sampling Clock Periods”).
b5b4
RW
(Note 3)
RW
(b7-b6)
Function
(Note 3)
Nothing is assigned. When write, set to “0”. When read, its
content is “0”.