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M16C/28 Group
Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
15. A-D Converter
Rev.0.60 2004.02.01
page 209 of N
REJ09B0047-0060Z
Figure 15.5 TB2SC Register
PWCOM
Symbol
Address
After reset
TB2SC
039E16
X00000002
Timer B2 Reload Timing
Switch Bit
0 : Timer B2 underflow
1 : Timer A output at odd-numbered
Timer B2 special mode register (Note 1)
Bit name
Function
Bit symbol
b7
b6
b5
b4
b3
b2
b1
b0
IVPCR1
Three-Phase Output Port
SD Control Bit 1
0 : Three-phase output forcible cutoff
by SD pin input (high impedance)
disabled
1 : Three-phase output forcible cutoff
by SD pin input (high impedance)
enabled
Note 1. Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enabled).
Note 2. If the INV11 bit is "0" (three-phase mode 0) or the INV06 bit is "1" (triangular wave modulation mode), set
this bit to "0" (timer B2 underflow).
RW
Nothing is assigned. When write, set to 0 .
When read, its content is 0 .
(b7)
TB2SEL
Trigger Select Bit
0 : TB2 interrupt
1 : Underflow of TB2 interrupt
generation frequency setting counter [ICTB2]
RW
TB0EN
Timer B0 Operation Mode
Select Bit
0 : Other than A-D trigger mode
1 : A-D trigger mode
RW
TB1EN
Timer B1 Operation Mode
Select Bit
0 : Other than A-D trigger mode
1 : A-D trigger mode
RW
Note 3. When setting the IVPCR1 bit to "1" (three-phase output forcible cutoff by SD pin input enabled), Set the PD8_5
bit to "0" (= input mode).
Note 4. Related pins are U(P80), U(P81), V(P72), V(P73), W(P74), W(P75). After forcible cutoff, input "H" to the P85/NMI/SD pin.
Set the IVPCR1 bit to "0", and this forcible cutoff will be reset. If L is input to the P85/NMI/SD pin, a three-phase motor
control timer output will be disabled (INV03=0). At this time, when the IVPCR1 bit is "0", the target pins changes to
programmable I/O port. When the IVPCR1 bit is "1", the target pins changes to high-impedance state regardless of
which functions of those pins are used.
Note 5. When this bit is used in delayed trigger mode 0, set the TB0EN and TB1EN bits to "1" (A-D trigger mode).
Note 6. When setting the TB2SEL bit to "1" (underflow of TB2 interrupt generation frequency setting counter[ICTB2]), Set the INV02
bit to "1" (three-phase motor control timer function).
Note 7. Refer to "17.6 Digital Debounce function" for the SD input
(Note 2)
(Note 3, 4, 7)
(Note 5)
(Note 6)
(b6-b5)
Reserved bits
Must set to "0"