M16C/28 Group
Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
7. Clock Generation Circuit
Rev.0.60 2004.02.01
page 33 of N
REJ09B0047-0060Z
0
System clock control register 0 (Note 1)
Symbol
Address
After reset
CM0
000616
010010002
Bit name
Function
Bit symbol
b7
b6
b5
b4
b3
b2
b1
b0
CM07
CM05
CM04
CM03
CM02
CM06
Wait Mode peripheral function
clock stop bit (Note 10)
0 : Do not stop peripheral function clock in wait mode
1 : Stop peripheral function clock in wait mode (Note 8)
XCIN-XCOUT drive capacity
select bit (Note 2)
0 : LOW
1 : HIGH
0 : I/O port P86, P87
1 : XCIN-XCOUT generation function(Note 9)
Main clock stop bit
(Notes 3, 10, 12, 13)
0 : On (Note 4)
1 : Off (Note5)
Main clock division select
bit 0 (Notes 7, 13, 14)
0 : CM16 and CM17 valid
1 : Division by 8 mode
System clock select bit
(Notes 6, 10, 11, 12)
0 : Main clock, PLL clock, or ring oscillator clock
1 : Sub-clock
Note 1: Write to this register after setting the PRC0 bit of PRCR register to ì1 (write enable).
Note 2: The CM03 bit is set to ì1 (high) when the CM04 bit is set to ì0 (I/O port) or the microcomputer goes to a stop mode.
Note 3: This bit is provided to stop the main clock when the low power dissipation mode or ring oscillator low power dissipation mode
is selected. This bit cannot be used for detection as to whether the main clock stopped or not. To stop the main clock, the
following setting is required:
(1) Set the CM07 bit to ì1 (Sub-clock select) or the CM21 bit of CM2 register to ì1 (Ring oscillator select) with the sub-cl ock
stably oscillating.
(2) Set the CM20 bit of CM2 register to ì0 (Oscillation stop, re-oscillation detection function disabled).
(3) Set the CM05 bit to ì1 (Stop) .
Note 4: During external clock input, set to "0"(On).
Note 5: When CM05 bit is set to ì1, the XOUT pin goes ìH. Furthermore, because the internal feedback resistor remains connected,
the XIN pin is pulled ìH to the same level as XOUT via the feedback resistor.
Note 6: After setting the CM04 bit to ì1 (X CIN-XCOUT oscillator function), wait until the sub-clock oscillates stably before switching
the CM07 bit from ì0 to ì1 (sub-clock).
Note 7: When entering stop mode from high or middle speed mode, ring oscillator mode or ring oscillator low power mode, the CM06
bit is set to ì1 (divide-by-8 mode).
Note 8: The fC32 clock does not stop. During low speed or low power dissipation mode, do not set this bit to ì1 (peripheral clock
turned off when in wait mode).
Note 9: To use a sub-clock, set this bit to ì1. Also make sure ports P8 6 and P87 are directed for input, with no pull-ups.
Note 10: When the PM21 bit of PM2 register is set to ì1 (clock modification disable), writing to the CM02, CM05, and CM07 bits has
no effect.
Note 11: If the PM21 bit needs to be set to ì1, set the CM07 bit to ì0(main clock) before setting it.
Note 12: To use the main clock as the clock source for the CPU clock, follow the procedure below.
(1) Set the CM05 bit to ì0 (oscillate) .
(2) Wait until td(M-L) elapses or the main clock oscillation stabilizes, whichever is longer.
(3) Set the CM11, CM21 and CM07 bits all to ì0.
Note 13: When the CM21 bit = 0 (ring oscillaor turned off) and the CM05 bit = 1 (main clock turned off), the CM06 bit is fixed to "1"
(divide-by-8 mode) and the CM15 bit is fixed to "1" (drive capability High).
Note 14: To return from ring oscillator mode to high-speed or middle-speed mode set the CM06 and CM15 bits both to "1".
RW
Port XC select bit
(Note 2)
RW
Reserved bits
Must set to "0"
(b1-b0)
0
Figure 7.2. CM0 Register