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M16c/28 Group
Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
14.2 SI/O 3 and SI/O 4
Rev.0.60 2004.02.01
page 200 of N
REJ09B0047-0060Z
SI/Oi bit rate generator (i = 3, 4) (Notes 1, 2)
b7
b0
Symbol
Address
After reset
S3BRG
036316
??16
S4BRG
036716
??16
Description
Assuming that set value = n, BRGi divides the count
source by n + 1
0016 to FF16
Setting range
RW
SI/Oi transmit/receive register (i = 3, 4) (Note 1, 2)
b7
b0
Symbol
Address
After reset
S3TRR
036016
??16
S4TRR
036416
??16
Description
Transmission/reception starts by writing transmit data to this register. After
transmission/reception finishes, reception data can be read by reading this register.
Note 1: Write to this register while serial I/O is neither transmitting nor receiving.
Note 2: To receive data, set the corresponding port direction bit for SINi to “0” (input mode).
S I/Oi control register (i = 3, 4) (Note 1)
Symbol
Address
After reset
S3C
036216
01000002
S4C
036616
01000002
b7
b6
b5
b4
b3 b2
b1
b0
Description
SMi5
SMi1
SMi0
SMi3
SMi6
SMi7
Internal synchronous
clock select bit
Transfer direction select
bit
S I/Oi port select bit
SOUTi initial value
set bit
0 0 : Selecting f1SIO or f2SIO
0 1 : Selecting f8SIO
1 0 : Selecting f32SIO
1 1 : Must not be set.
b1 b0
0 : External clock
1 : Internal clock
Effective when SMi3 = 0
0 : “L” output
1 : “H” output
0 : Input/output port
1 : SOUTi output, CLKi function
Bit name
Bit
symbol
Synchronous clock
select bit
0 : LSB first
1 : MSB first
SMi2
SOUTi output disable bit
0 : SOUTi output
1 : SOUTi output disable(high impedance)
Note 1: Make sure register S4C is written to by the next instruction after setting the PRCR register's PRC2 bit to “1"
(write enable).
Note 2: Set the SMi3 bit to “1” (SOUTi output, CLKi function).
Note 3: Set the SMi3 bit to “1” and the corresponding port direction bit to “0” (input mode).
Note 4: Effective when SMi3 bit = 1.
CLK polarity select bit
SMi4
0 : Transmit data is output at falling edge of
transfer clock and receive data is input at
rising edge
1 : Transmit data is output at rising edge of
transfer clock and receive data is input at
falling edge
RW
WO
RW
(Note 4)
(Note 2)
(Note 3)
Note 1: Write to this register while serial I/O is neither transmitting nor receiving.
Note 2: Use MOV instruction to write to this register.
Figure 14.2.2. S3C and S4C Registers, S3BRG and S4BRG Registers, and S3TRR and S4TRR Registers