參數(shù)資料
型號: M30240M4-XXXFP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, MICROCONTROLLER, PQFP80
封裝: 0.80 MM PITCH, PLASTIC, QFP-80
文件頁數(shù): 83/125頁
文件大?。?/td> 753K
代理商: M30240M4-XXXFP
CONFIDENTIAL
62
Mitsubishi microcomputers
M16C / 24 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change
DMAC
(1) Transfer cycle
The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area
(source read) and the bus cycle in which the data is written to memory or to the SFR area (destination
write). The number of read and write bus cycles depends on the source and destination addresses
and the software waits are inserted.
(a) Effect of source and destination addresses
When 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd address-
es, there is one more source read cycle and destination write cycle than when the source and destination both
start at even addresses.
(2) DMAC transfer cycles
Any combination of even or odd transfer read and write addresses is possible. Table 14 show the num-
ber of DMAC transfer cycles. Table 15 shows the corresponding coefficient values. Figure 57 shows
an example of the transfer cycle for a source read.
The number of DMAC transfer cycles can be calculated as follows:
Number of transfer cycles per transfer unit = Number of read cycles x j + Number of write cycles x k
Table 14:
Number of DMAC transfer cycles
Transfer unit
Access
address
Single-chip mode
Number of
read cycles
Number of
write cycles
8-bit transfers
(DMBIT=”1”)
Even
1
Odd
1
16-bit transfers
(DMBIT=”0”)
Even
1
Odd
2
Table 15:
Coefcients j,k
Internal memory
Internal ROM/
RAM No wait
Internal ROM/
RAM with wait
SFR area
122
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