- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45010 > M30240M4-XXXFP 16-BIT, MROM, MICROCONTROLLER, PQFP80 PDF資料下載
參數(shù)資料
| 型號(hào)： | M30240M4-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, MICROCONTROLLER, PQFP80 |
| 封裝： | 0.80 MM PITCH, PLASTIC, QFP-80 |
| 文件頁(yè)數(shù)： | 124/125頁(yè) |
| 文件大?。?/td> | 753K |
| 代理商： | M30240M4-XXXFP |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)當(dāng)前第124頁(yè)第125頁(yè)
CONFIDENTIAL
100
Mitsubishi microcomputers
M16C / 24 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change
UART0 through UART2
(3) Clock-asynchronous serial I/O mode (compliant with the SIM interface)
The SIM interface is used for connecting the microcomputer with a memory card I/C or the like; adding
some extra settings in UART2 clock-asynchronous serial I/O mode allows the user to effect this func-
tion. Table 29 shows the specifications of clock-asynchronous serial I/O mode (compliant with the SIM
interface). Figure 94 shows the typical transmit/receive timing in UART mode.
Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UARTi bit rate generator.
Note 2: fEXT is input from the CLK2 pin.
Note 3: If an overrun error occurs, the UART2 receive buffer will have the next data written in. Note also that the UARTi
receive interrupt request bit is not set to “1”.
Table 29:
Specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface)
Item
Specication
Transfer data
format
Transfer data 8-bit UART mode (bit 2 through bit 0 of address 037816 = “1012”)
One stop bit (bit 4 of address 037816 = “0”)
With the direct format chosen
Set parity to “even” (bit 5 and bit 6 of address 037816 = “1” and “1” respectively)
Set data logic to “direct” (bit 6 of address 037D16 = “0”).
Set transfer format to LSB (bit 7 of address 037C16 = “0”).
With the inverse format chosen
Set parity to “odd” (bit 5 and bit 6 of address 037816 = “0” and “1” respectively)
Set data logic to “inverse” (bit 6 of address 037D16 = “1”)
Set transfer format to MSB (bit 7 of address 037C16 = “1”)
Transfer clock
With the internal clock chosen (bit 3 of address 037816 = “0”) : / 16 (n + 1) (Note 1) : =f1, f8, f32
With an external clock chosen (bit 3 of address 037816 = “1”) : fEXT / 16 (n+1) (Note 1) (Note 2)
Transmission /
reception control
Disable the CTS and RTS function (bit 4 of address 037C16 = “1”)
Other settings
The sleep mode select function is not available for UART2
Set transmission interrupt factor to “transmission completed” (bit 4 of address 037D16 = “1”)
Transmission
start condition
To start transmission, the following requirements must be met:
- Transmit enable bit (bit 0 of address 037D16) = “1”
- Transmit buffer empty ag (bit 1 of address 037D16) = “0”
Reception start
condition
To start reception, the following requirements must be met:
- Reception enable bit (bit 2 of address 037D16) = “1”
- Detection of a start bit
When transmitting
When data transmission from the UART2 transfer register is completed (bit 4 of address 037D16 =
“1”)
When receiving
When data transfer from the UART2 receive register to the UART2 receive buffer register is
completed
Error detection
Overrun error (see the specications of clock-asynchronous serial I/O) (Note 3)
Framing error (see the specications of clock-asynchronous serial I/O)
Parity error (see the specications of clock-asynchronous serial I/O)
- On the reception side, an “L” level is output from the TxD2 pin by use of the parity error signal
output function (bit 7 of address 037D16 = “1”) when a parity error is detected
- On the transmission side, a parity error is detected by the level of input to the RxD2 pin when a
transmission interrupt occurs
The error sum ag (see the specications of clock-asynchronous serial I/O)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M30240M1-XXXFP | 16-BIT, MROM, MICROCONTROLLER, PQFP80 |
| M30245MC-XXXGP | 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP100 |
| M30245FCGP | 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP100 |
| M30260F3VGP | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP48 |
| M30260M3A-XXXGP-U5 | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP48 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M30240M5 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30240M5-XXXFP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30240M6 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30240M6-XXXFP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30240M7 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。