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| 型號(hào)： | M30240M4-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, MICROCONTROLLER, PQFP80 |
| 封裝： | 0.80 MM PITCH, PLASTIC, QFP-80 |
| 文件頁(yè)數(shù)： | 69/125頁(yè) |
| 文件大小： | 753K |
| 代理商： | M30240M4-XXXFP |
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CONFIDENTIAL
50
Mitsubishi microcomputers
M16C / 24 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change
Universal Serial Bus
USB Suspend Detection Flag
When the USB FCU receives a USB suspend signaling, it sets the SUSPEND bit and generates an
interrupt. The CPU writes a “0” to clear this bit when the device is resumed by the host (resume inter-
rupt is generated and Resume Detection Flag is set) or remote wake-up by itself (The CPU writes a
“1” to Remote Wake-up Bit).
USB Resume Detection Flag
When the USB FCU is in suspend mode and receives a USB resume signaling, it sets the RESUME
bit, and generates an interrupt. The CPU writes a “0” to clear this bit.
USB Remote Wake-up Bit
The CPU writes a “1” to the WAKEUP bit for remote wake-up. While this bit is set, and the USB FCU
is in suspend mode, it generates a resume signaling to the host. The CPU must keep this bit set for a
minimum of 10ms and a maximum of 15ms before writing a “0” to this bit.
The USB FCU is able to generate a USB function interrupt as discussed in “USB Interrupt” section .
USB Interrupt Status Registers, shown in Figures 34 and 35, are used to indicate the condition that
caused a USB function interrupt to the CPU. A “1” indicates the corresponding condition caused a
USB function interrupt. The USB Interrupt Status Registers can be cleared by writing back to the reg-
ister the same value that was read. To ensure proper operation, the CPU reads both USB interrupt
status registers, then write back the same values it read to these two registers for clearing the status
bits. The CPU must write the USB Interrupt Status Register 1 first, then the USB Interrupt Status
Register 2. The registers cannot be cleared by writing a “0” to the bits that are a “1”.
Figure 34:
USB Interrupt Status Register 1
INTST0 is set to a “1” by the USB FCU if (in Endpoint 0 CSR):
Successfully receives a packet of data
Successfully sends a packet of data
EP0CSR3 (DATA_END) bit is cleared
EP0CSR4 (FORCE_STALL) bit is set
EP0CSR5 (SETUP_END) bit is set
INTST2, INTST4, INTST6 or INTST8 is set to a “1” by the USB FCU if (in Endpoint x IN CSR):
Successfully sends a packet of data
INXCSR1 (UNDER_RUN) bit is set
INTST0
USB Endpoint 0 Interrupt Status Flag (bit 0)
Bit 1
Reserved (Read/Write “0”)
INTST2
USB Endpoint 1 IN Interrupt Status Flag (bit 2)
INTST3
USB Endpoint 1 OUT Interrupt Status Flag (bit 3)
INTST4
USB Endpoint 2 IN Interrupt Status Flag (bit 4)
INTST5
USB Endpoint 2 OUT Interrupt Status Flag (bit 5)
INTST6
USB Endpoint 3 IN Interrupt Status Flag (bit 6)
INTST7
USB Endpoint 3 OUT Interrupt Status Flag (bit 7)
0: No interrupt request issued
1: Interrupt request issued
MSB
7
LSB
0
INTST7
INTST6
INTST5
INTST4
INTST3
Reserved
INTST0
Access: R/W
Reset:
0016
INTST2
Address: 030216
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M30240M1-XXXFP | 16-BIT, MROM, MICROCONTROLLER, PQFP80 |
| M30245MC-XXXGP | 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP100 |
| M30245FCGP | 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP100 |
| M30260F3VGP | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP48 |
| M30260M3A-XXXGP-U5 | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP48 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M30240M5 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30240M5-XXXFP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30240M6 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30240M6-XXXFP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30240M7 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
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