參數(shù)資料
型號(hào)： M30240M4-XXXFP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, MICROCONTROLLER, PQFP80
封裝： 0.80 MM PITCH, PLASTIC, QFP-80
文件頁數(shù)： 73/125頁
文件大?。?/td> 753K
代理商： M30240M4-XXXFP
Mitsubishi microcomputers
M16C / 24 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
53
CONFIDENTIAL
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change
Universal Serial Bus
Figure 40:
USB ISO Control Register
The USB DMAx Request Registers, shown in Figures 41 and 42, are used to select the USB Endpoint x FIFO
read/write request as DMAC channel 0 or channel 1 request source. Figure 43 shows the USB enpoint enable
register. The USB DMA0 (DMA1) Request Register has only one bit set at any given time. If multiple bits are set,
then no request is selected
.
Figure 41:
USB DMA0 Request Register
Figure 42:
USB DMA1 Request Register
Figure 43:
USB Endpoint enable register
Bits 5:0
Reserved (Read/Write “0”)
AUTO_FL
AUTO_FLUSH Bit (bit 6)
0: Hardware auto FIFO ush disabled
1: Hardware auto FIFO ush enabled
ISO_UPD
ISO_UPDATE Bit (bit 7)
0: ISO_UPDATE disabled
1: ISO_UPDATE enabled
MSB
7
LSB
0
ISO_UPD AUTO_FL Reserved Reserved Reserved
Reserved Reserved
Access: R/W
Reset:
0016
Address: 030816
Reserved
DMA0R0
Endpoint 1 IN FIFO Write Request Selection bit (bit 0)
DMA0R1
Endpoint 2 IN FIFO Write Request Selection bit (bit 1)
DMA0R2
Endpoint 3 IN FIFO Write Request Selection bit (bit 2)
DMA0R3
Endpoint 4 IN FIFO Write Request Selection bit (bit 3)
DMA0R4
Endpoint 1 OUT FIFO Read Request Selection bit (bit 4)
DMA0R5
Endpoint 2 OUT FIFO Read Request Selection bit (bit 5)
DMA0R6
Endpoint 3 OUT FIFO Read Request Selection bit (bit 6)
DMA0R7
Endpoint 4 OUT FIFO Read Request Selection bit (bit 7)
0: Not selected
1: Selected
MSB
7
LSB
0
DMA0R7
DMA0R6
DMA0R5
DMA0R4
DMA0R3
DMA0R1
DMA0R0
Access: R/W
Reset:
0016
DMA0R2
Address: 030916
DMA1R0
Endpoint 1 IN FIFO Write Request Selection bit (bit 0)
DMA1R1
Endpoint 2 IN FIFO Write Request Selection bit (bit 1)
DMA1R2
Endpoint 3 IN FIFO Write Request Selection bit (bit 2)
DMA1R3
Endpoint 4 IN FIFO Write Request Selection bit (bit 3)
DMA1R4
Endpoint 1 OUT FIFO Read Request Selection bit (bit 4)
DMA1R5
Endpoint 2 OUT FIFO Read Request Selection bit (bit 5)
DMA1R6
Endpoint 3 OUT FIFO Read Request Selection bit (bit 6)
DMA1R7
Endpoint 4 OUT FIFO Read Request Selection bit (bit 7)
0: Not selected
1: Selected
MSB
7
LSB
0
DMA1R7
DMA1R6
DMA1R5
DMA1R4
DMA1R3
DMA1R1
DMA1R0
Access: R/W
Reset:
0016
DMA1R2
Address: 030A16
MSB
7
EP4_IN
EP4_OUT
EP3_IN
EP3_OUT
EP2_IN
EP1_IN
EP1_OUT
Access: R/W
Reset:
ff16
EP2_OUT
Address: 030B16
LSB
0
0: Not selected
1: Selected
EP1_OUT
Endpoint 1 IN FIFO Write Request Selection bit (bit 0)
EP1_IN
Endpoint 2 IN FIFO Write Request Selection bit (bit 1)
EP2_OUT
Endpoint 3 IN FIFO Write Request Selection bit (bit 2)
EP2_IN
Endpoint 4 IN FIFO Write Request Selection bit (bit 3)
EP3_OUT
Endpoint 1 OUT FIFO Read Request Selection bit (bit 4)
EP3_IN
Endpoint 2 OUT FIFO Read Request Selection bit (bit 5)
EP4_OUT
Endpoint 3 OUT FIFO Read Request Selection bit (bit 6)
EP4-IN
Endpoint 4 OUT FIFO Read Request Selection bit (bit 7)
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