參數(shù)資料
型號: M30240M4-XXXFP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, MICROCONTROLLER, PQFP80
封裝: 0.80 MM PITCH, PLASTIC, QFP-80
文件頁數(shù): 41/125頁
文件大小: 753K
代理商: M30240M4-XXXFP
CONFIDENTIAL
24
Mitsubishi microcomputers
M16C / 24 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change
Clock Control
2.8 Clock Control
Figure 12 shows the block diagram of the clock-generating circuit.
Figure 12:
Clock-generating circuit
The following paragraphs describes the clocks generated by the clock-generating circuit.
(1) Main clock
The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by
8 to the internal clock
φ. The clock can be stopped using the main clock stop bit (bit 5 at address
000616). Stopping the clock reduces the power dissipation.
After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the XOUT
pin can be reduced using the XIN-XOUT drive capacity select bit (bit 5 at address 000716). Reducing
the drive capacity of the XOUT pin reduces the power dissipation. This bit defaults to “1” when shifting
to stop mode and after a reset.
(2) Internal clock
φ
The internal clock
φ is the clock that drives the CPU, and is either the main clock or is derived by di-
viding the main clock by 2, 4, 8, or 16. The internal clock
φ is derived by dividing the main clock by 8
after a reset.
CM0i : Bit i at address 000616
CM1i : Bit i at address 000716
WAIT instruction
CM02
Q
S
R
NMI
Interrupt request
level judgment
output
RESET
Software reset
fAD
Divider
a
d
1/2
CM06=0
CM17,CM16=00
CM06=0
CM17,CM16=01
CM06=0
CM17,CM16=10
CM06=1
CM06=0
CM17,CM16=11
d
a
Details of divider
c
b
1/2
c
f1
f32SIO2
f8SIO2
f1SIO2
f8
f32
φ
XOUT
Main clock
CM10 “1”
Write signal
Q
S
R
XIN
Frequency
Multiplier
fusb (48MHz)
FSCCR0=1
FSCCR0=0
Internal clock
φ
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