參數(shù)資料
型號: M30240M4-XXXFP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, MICROCONTROLLER, PQFP80
封裝: 0.80 MM PITCH, PLASTIC, QFP-80
文件頁數(shù): 122/125頁
文件大小: 753K
代理商: M30240M4-XXXFP
CONFIDENTIAL
98
Mitsubishi microcomputers
M16C / 24 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change
UART0 through UART2
Figure 90:
Typical receive timing in UART mode
(a) Separate CTS/RTS pins function (UART0)
With the separate CTS/RTS bit (bit 6 at address 03B016) is set to “1”, the unit outputs/inputs the CTS and RTS
signals on different pins. (See Figure 91.) This function is valid only for UART0. Note that if this function is
selected, the CTS/RTS function for UART1 cannot be used.
Figure 91:
The separate CTS/RTS pins function usage
(b) Sleep mode (UART0, UART1)
This mode is used to transfer data between specific microcomputers among multiple microcomputers con-
nected using UARTi. The sleep mode is selected when the sleep select bit (bit 7 at addresses 03A016,
03A816) is set to “1” during reception. In this mode, the unit performs receive operation when the MSB of the
received data = “1” and does not perform receive operation when the MSB = “0”.
D0
Start bit
Sampled “L”
Receive data taken in
BRGi count
source
Receive enable bit
RxDi
Transfer clock
Receive
complete flag
RTSi
Stop bit
“1”
“0”
“1”
“H”
“L”
The above timing applies to the following settings :
Parity is disabled.
One stop bit.
RTS function is selected.
Receive interrupt
request bit
“0”
“1”
Transferred from UARTi receive register to
UARTi receive buffer register
Reception triggered when transfer clock
is generated by falling edge of start bit
D7
D1
Cleared to “0” when interrupt request is accepted, or cleared by software
Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
Microcomputer
TXD0 (P63)
RXD0 (P62)
IN
OUT
CTS
RTS
CTS0 (P64)
RTS0 (P60)
IC
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