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| 型號(hào)： | M30240M4-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, MICROCONTROLLER, PQFP80 |
| 封裝： | 0.80 MM PITCH, PLASTIC, QFP-80 |
| 文件頁(yè)數(shù)： | 79/125頁(yè) |
| 文件大?。?/td> | 753K |
| 代理商： | M30240M4-XXXFP |
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Mitsubishi microcomputers
M16C / 24 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
59
CONFIDENTIAL
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change
DMAC
2.19 DMAC
This microcomputer has two DMAC (direct memory access controller) channels that allow data to be
sent to memory without using the CPU.Table 13 shows the DMAC specifications. Figure 53 shows the
block diagram of the DMAC. Figure 54, Figure 55 and Figure 56 show the registers used by the DMAC.
Note:DMA transfer is not affected by any interrupt.
Table 13:
DMAC specications
Item
Specication
Number of channels
2 (cycle steal method)
Transfer memory space
From any SFR, RAM, or ROM address to a xed address
From a xed address to any SFR or RAM address
From a xed address to a xed address
(Note that DMA-related registers [002016 to 003F16] cannot be accessed)
Maximum number of bytes
transferred
128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)
DMA request factors (Note)
Falling edge of INT0 or INT1 (INT0 can be selected by DMA0, INT1 by DMA1)
Timer A0 to timer A4 interrupt requests
Timer B0 to timer B1 interrupt requests
UART0 transmission and reception interrupt requests
UART1 transmission and reception interrupt requests
UART2 transmission and reception interrupt requests
A-D conversion interrupt requests
USB function interrupt requests
USB SOF interrupt requests
Software triggers
Channel priority
DMA0 takes precedence if DMA0 and DMA1 requests are generated simultaneously
Transfer unit
8 bits or 16 bits
Transfer address direction
forward/xed (forward direction cannot be specied for both source and destination
simultaneously)
Transfer mode
Single transfer
The DMA enable bit is cleared and transfer ends when an underow occurs in the
transfer counter
Repeat transfer
When an underow occurs in the transfer counter, the value in the transfer counter
reload register is reloaded into the transfer counter and the DMA transfer is repeated
DMA interrupt request generation
timing
When an underow occurs in the transfer counter
DMA startup
Single transfer
Transfer starts when the DMA is requested after “1” is written to the DMA enable bit
Repeat transfer
Transfer starts when the DMA is requested after “1” is written to the DMA enable bit
or after an underow occurs in the transfer counter
DMA shutdown
When “0” is written to the DMA enable bit
When, in single transfer mode, an underow occurs in the transfer counter
Forward address pointer and
reload timing for transfer counter
When DMA transfer starts, the value of whichever of the source or destination pointer that is set
up as the forward pointer is reloaded into the forward address pointer. The value in the transfer
counter reload register is reloaded into the transfer counter.
Writing to register
Registers specied for forward direction transfer are always write-enabled.
Registers specied for xed address transfer are write-enabled when the DMA enable bit is “0”.
Reading the register
Can be read at any time.
However, when the DMA enable bit is “1”, reading the register sets up as the forward
register is the same as reading the value of the forward address pointer.
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相關(guān)代理商/技術(shù)參數(shù) |
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| M30240M5 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30240M5-XXXFP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
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| M30240M6-XXXFP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30240M7 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
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