參數(shù)資料
型號(hào)： M30240M4-XXXFP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, MICROCONTROLLER, PQFP80
封裝： 0.80 MM PITCH, PLASTIC, QFP-80
文件頁(yè)數(shù)： 125/125頁(yè)
文件大?。?/td> 753K
代理商： M30240M4-XXXFP
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Mitsubishi microcomputers
M16C / 24 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
101
CONFIDENTIAL
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change
UART0 through UART2
Figure 94:
Typical transmit/receive timing in UART mode (compliant with the SIM interface)
Transmit enable
bit(TE)
Transmit buffer
empty flag(TI)
Transmit register
empty flag (TXEPT)
D0 D1
D2 D3 D4 D5 D6 D7
ST
P
Start
bit
Parity
bit
The above timing applies to the following settings :
Parity is enabled.
One stop bit.
Transmit interrupt cause select bit = “1”.
“0”
“1”
“0”
“1”
“0”
“1”
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of BRGi count source (f1, f8, f32)
fEXT : frequency of BRGi count source (external clock)
n : value set to BRGi
Transmit interrupt
request bit (IR)
“0”
“1”
D0 D1
D2 D3 D4 D5 D6 D7
ST
P
Shown in ( ) are bit symbols.
Tc
Transfer clock
SP
Stop
bit
Data is set in UARTi transmit buffer register
SP
A “L” level returns from TxD2 due to
the occurrence of a parity error.
The level is detected by the
interrupt routine.
The level is
detected by the
interrupt routine.
Receive enable
bit (RE)
Receive complete
flag (RI)
D0 D1
D2 D3 D4 D5 D6 D7
ST
P
Start
bit
Parity
bit
TxD2
The above timing applies to the following settings :
Parity is enabled.
One stop bit.
Transmit interrupt cause select bit = “0”.
“0”
“1”
“0”
“1”
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of BRGi count source (f1, f8, f32)
fEXT : frequency of BRGi count source (external clock)
n : value set to BRGi
Receive interrupt
request bit (IR)
“0”
“1”
D0 D1
D2 D3 D4 D5 D6 D7
ST
P
SP
Shown in ( ) are bit symbols.
Tc
Transfer clock
SP
Stop
bit
A “L” level returns from TxD2 due to
the occurrence of a parity error.
RxD2
Read to receive buffer
D0 D1 D2 D3 D4 D5 D6 D7
ST
P
Signal conductor level
(Note 1)
D0 D1
D2 D3 D4 D5 D6 D7
ST
P
SP
D0 D1
D2 D3 D4 D5 D6 D7
ST
P
D0 D1
D2 D3
D4 D5 D6
D7
ST
P
SP
TxD2
RxD2
Signal conductor level
(Note 1)
Note: Equal in waveform because TxD2 and RxD2 are connected.
Transferred from UARTi transmit buffer register to UARTi transmit register
Cleared to “0” when interrupt request is accepted, or cleared by software
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