參數(shù)資料
型號： M30240M4-XXXFP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, MICROCONTROLLER, PQFP80
封裝： 0.80 MM PITCH, PLASTIC, QFP-80
文件頁數(shù)： 4/125頁
文件大?。?/td> 753K
代理商： M30240M4-XXXFP
Mitsubishi microcomputers
M16C / 24 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
103
CONFIDENTIAL
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change
A-D Converter
2.24 A-D Converter
The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a
capacitive coupling amplifier. Pins P100 to P107 function as the analog signal input pins. The direction
registers of these pins for A-D conversion must therefore be set to input. The Vref connect bit (bit 5 at
address 03D716) can be used to isolate the resistance ladder of the A-D converter from the reference
voltage input pin (VREF) when the A-D converter is not used. Doing so stops any current flowing into
the resistance ladder from VREF, reducing the power dissipation. When using the A-D converter, start
A-D conversion only after setting bit 5 of 03D716 to connect VREF.
The result of A-D conversion is stored in the A-D registers of the selected pins. When set to 10-bit
precision, the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When
set to 8-bit precision, the low 8 bits are stored in the even addresses.
Table 30 shows the performance of the A-D converter. Figure 98 shows the block diagram of the A-D
converter, and Figure 99 and Figure 100 show the A-D converter-related registers.
r
Table 30:
Performance of A-D Converter
Item
Performance
Method of A-D conversion
Successive approximation (capacitive coupling amplier)
Analog input voltage (Note 1)
0V to AVCC (VCC)
Operating clock fAD (Note 2)
VCC = 5V
fAD/divide-by-2 or fAD/divide-by-4 or fAD, fAD=f(XIN)
Resolution
8-bit or 10-bit (selectable)
Absolute precision
VCC = 5V
Without sample and hold function
3LSB
With sample and hold function (8-bit resolution)
2LSB
With sample and hold function (10-bit resolution)AN0 to AN7 input
3LSB
Operating modes
One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, and
repeat sweep mode 1
Analog input pins
8pins (AN0 to AN7)
A-D conversion start condition
Software trigger
A-D conversion starts when the A-D conversion start ag changes to “1”
External trigger (can be retriggered)
A-D conversion starts when the A-D conversion start ag is “1” and the ADTRG/P87
input changes from “H” to “L”
Conversion speed per pin
Without sample and hold function
8-bit resolution: 49
φAD cycles, 10-bit resolution: 59 φAD cycles
With sample and hold function
8-bit resolution: 28
φAD cycles, 10-bit resolution: 33 φAD cycles
Note 1 Does not depend on use of sample and hold function.
Note 2 Without sample and hold function, set the 0AD frequency to 250 kHz minimum;
with sample and hold function, set the 0AD frequency to 1 MHz minimum.
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