
IX-24
Index
PREQn signal
2-5
description
2-5
timing
11-17
usage overview
10-26
Presentation Time Stamp
A-10
presentation units synchronized
4-3
priority interrupts
4-11
,
5-10
private_2 stream packet data errors
6-22
processing rate
4-52
,
4-55
program counter
4-57
program streams
6-1
error handling
6-21
to
6-24
preparsing
6-9
,
6-18
system channel buffer map
6-19
programmable background Y/Cb/Cr bits
4-60
programmable delay
4-43
programs
6-1
progressive frame (defined)
9-16
PS
B-7
PSI
B-7
psychoacoustic modeling
A-8
PTS
B-7
pulldown control
8-41
,
9-38
,
9-39
pulldown operation timing
9-39
PXD
B-7
Q
Q table
8-14
address bits
4-56
entry availability
4-57
ready bit
4-56
quality (images)
9-16
quant matrix extension
8-13
,
8-14
quantization intervals
A-3
quantization level
A-4
quantization values
4-88
linear PCM streams
10-15
MPEG samples
10-3
,
10-12
PCM samples
10-16
quantizer scale
A-6
changes
A-6
R
RAM
B-7
RAM test registers
4-91
operational mode
4-91
output select
4-92
status
4-93
range control
4-87
,
10-17
raster mapper
9-22
rate control (automatic)
8-43
,
8-44
rate matching
1-5
RDYn signal
2-4
description
2-4
read pointers
1-3
audio DTS compare
4-29
audio ES channel buffer end address
10-7
audio ES channel reset
4-20
audio sync code address
4-31
auxiliary data
8-21
buffer start
6-28
comparison enables
4-21
current address
4-4
audio ES channel buffer
4-28
video ES channel buffer
4-27
elementary stream mode
6-14
external SDRAM
6-27
picture start code
4-31
S/P DIF buffer reset
4-20
transport streams
6-25
user data
8-24
video DTS compare
4-28
video ES channel reset
4-20
READ signal
2-4
description
2-4
read/write strobe
2-4
READn signal
2-4
description
2-4
reads
A/V data
6-8
audio items remaining
4-33
Aux data FIFO port
4-19
Aux data layer
4-18
decimation filter and
9-20
DMA controller
5-15
,
5-17
starting addresses
4-46
FIFO
1-3
FIFO status
4-38
frame stores
9-6
,
9-30
host
2-3
,
4-41
host flowchart
5-13
Intel mode timing
5-5
diagram
11-13
Motorola mode timing
5-4
diagram
11-11
number of pictures in video ES buffer
4-38
OSD palette
4-60
Q table
4-56
,
4-57
,
8-14
ready interrupt
4-2
scan line display
4-65
SCR counter
5-7
SDRAM
4-47
,
5-10
to
5-13
,
7-2
,
9-2
starting addresses
4-42
SDRAM timing cycle
7-4
SDRAM timing diagram
11-7