
Clock Divider
10-33
32, 44.1, and 48 kHz sampling rates. The inputs to these must be the
sampling rate times N, where N can be 256, 384, 512, or 768. The N
value must be an integral multiple of the sample resolution (16, 20, or
24). Any or all of the inputs can be connected depending on the audio
sampling rates and resolutions expected.
At reset and power on, the L64105 defaults to using the clock supplied
on the ACLK_ 48 pin. The host selects the ACLK_ input pin by
programming the ACLK Select [1:0] bits in Register 363 (
page 4-84
). The
host also selects the divisor values used in the Clock Divider by
programming the ACLK Divider Select [3:0] bits in Register 364.
The divisor values depend on ACLK_ availability, the input audio
sampling frequency (Fs), the sample resolution (16/24/32 bits per
sample), and the external DAC capabilities. The equations for the derived
clocks are:
S/P DIF BCLK = Fs * sample resolution * 2 channels * 2 marks
= Fs * 32 * 4
= Fs * 128
DAC BCLK
= Fs * sample resolution * 2 channels
= Fs * 32 * 2
= Fs * 64
A_ACLK
= Fs * sample resolution * K
= Fs * 256 or Fs * 384
The ACLK Divider Select bit selections and the resulting clocks are listed
in
Table 10.11
. Use the following cases as selection criteria:
Case I: All of the ACLK_ inputs are available. Select the ACLK_
which is a multiple of the input sampling frequency using bits 0 and
1 in Register 363. Then use the 0x0 through 0x4 ACLK Divider
Select code that matches the Fs multiple of the ACLK_. For example,
if the input sampling frequency is 32 kHz and ACLK_32 =
512 * 32 kHz, use the 0x2 ACLK Divider Select code.
Case IIA: The Linear PCM bitstream with a sampling frequency of
96 kHz is selected and the external DAC supports 96-kHz sampling
frequency. ACLK_48 at a multiple of 512 or 768 must be available
and it must be selected. Use divider code 0x5 for ACLK = 768 * 48
and code 0x6 for ACLK = 512 * 48.