
Video Interface Registers
4-63
Odd/Not Even Field
R 6
The display controller sets this bit at the first horizontal
sync after a vertical sync during an odd field. This bit is
cleared at the first horizontal sync after a vertical sync
during an even field.
Top/Not Bottom Field
R 7
This bit is set at the first horizontal sync after a vertical
sync when top-field data is being displayed. This bit is
cleared at the first horizontal sync after a vertical sync
when bottom-field data is being displayed.
Figure 4.93
Register 276 (0x114)
Last Field
R 0
When set, this bit indicates that the current field being
displayed is the last field in the frame.
Horizontal Filter Enable
R/W 1
Setting this bit enables the horizontal interpolation filter.
Horizontal Filter Select
R/W 2
This bit sets the frequency response of the output filter to
one of two preprogrammed values. When this bit is 1,
frequency response ‘A’ is selected; when the bit is 0,
frequency response ‘B’ is selected. See
Section 9.8,
“Horizontal Postprocessing Filters,”
for more details.
Display Mode [3:0]
R/W [6:3]
The host should encode these bits based on the
characteristics of the source video as shown in
Table 4.1
.
These bits cause the display controller to operate in one
of 12 different postprocessing modes. Refer to
Section
9.6, “Display Modes and Vertical Filtering,”
for
descriptions of each of these modes.
7
6
3
2
1
0
Field Sync
Enable
Display Mode [3:0]
Horizontal
Filter Select
Horizontal
Filter Enable
Last Field