
Register Access and Functions
5-7
In the No Compare and Capture mode, the SCR counter can be read,
paused, and loaded by the host through the SCR Value registers. The
L64105 only keeps the LSB in Register 9 updated. When the host reads
the LSB, the upper three bytes of the counter are captured and written
to Registers 10, 11, and 12. To load a value into the counter, the host
must set the SCR Pause bit in Register 7, write the new counter value
in the SCR Value registers, and then clear the SCR Pause bit. The SCR
counter then increments from the value in the SCR Value registers.
Also in this mode, when the SCR counter overflows, the SCR Overflow
Interrupt bit in Register 1 is set and the INTRn output to the host is
asserted if not masked by the host for this interrupt.
Figure 5.6
Operation of the SCR Counter
SCR Counter
SCR Temporary Holding
LSB
MSB
Overflow Interrupt
SCR Pause
(Register 7)
=
SCR Compare Audio Registers (R/W)
Compare
Mode
(Register 17)
Autostart
Audio
Load
...
Picture Start
Code Event
Audio Sync
Code Event
DTS Video
Event
Capture
Mode
Other Events
Divided Clock
SCR Value Registers (R/W)
Register 9
Register 10
Register 11
Register 12
LSB
MSB
Register 13
Register 14
Register 15
Register 16
SCR Compare/Capture Registers (R/W)
=
Audio Start
on Compare
(Register 19)
Autostart
Video
Video Start
on Compare
(Register 19)
LSB
MSB
(Register 17)
Compare
Mode
(Register 17)
SCR
Compare
Interrupt
Register 20
Register 21
Register 22
Register 23