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| 型號(hào)： | IDT88K8483BRI |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 99/162頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC SPI-4 EXCHANGE 3PORT 672-BGA |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | * |
| 其它名稱： | 88K8483BRI |
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October 20, 2006
IDT IDT88K8483
SPI-4 Interface
Overview
SPI-4.2 as originally defined is an interface for packet and cell transfer between a physical layer (PHY) device and a link layer device (network
processor), for aggregate bandwidths of OC-192 ATM and Packet over SONET/SDH (POS), as well as 10 Gb/s Ethernet applications. The SPI-4.2
protocol transfers data in variable length bursts. Associated with each burst is information such as logical port number (for a multi-port device such as
a 10 x 1 GbE MAC), SOP, EOP. This information is collected by the SPI-4 interface and passed to the PFPs. The Optical Internetworking Forum (OIF)
controls the SPI-4.2 Implementation Agreement document (available at http://www.oiforum.com).
The SPI-4 interface power down mode has to be disabled before configuring the interface. The SPI-4 interface also has to be configured before the
interface is enabled. The SPI-4 interface LVDS outputs (except for the clock) can be powered down by setting to 1 the SPI4_PDN field in the SPI-4
Interface Enable Register (p. 106). The interface is enabled by setting to 1 the SPI4_EN field in the SPI-4 Interface Enable Register (p. 106).
The SPI-4 interface consists of separate ingress and egress interfaces as described in Figure 14 IDT88K8483 SPI-4 Connections
. The ingress and egress ports are unidirectional and independent of each other. Each port has 16 data signals, a clock, and a control
signal, all of which use LVDS (differential) signaling, and are sampled on both edges of the clock. There are also ingress status port and egress status
port. Each status port has 2 fifo status signals and a clock. The status port signal can be configured to LVDS (differential) or LVTTL by the status
channel control pin LVDSSTA (SPI4A_LVDSSTA, SPI4B_LVDSSTA, SPI4AM_LVDSSTA). The ingress port supports dynamic alignment, and the egress
port supports programmable skew.
The IDT88K8483 has three SPI-4 interfaces: one main SPI-4 interface (M) and two tributary SPI-4 interface (A and B). Each tributary SPI4 inter-
face supports up to 64 logical ports. The main SPI4 interface supports up to 128 logical ports. The logical port in-band address are from 0 to 255.
The clock source for the SPI-4 ingress port is the SPI-4 interface input clock IDCLK (SPI4A_IDCLK_P, SPI4A_IDCLK_N, SPI4B_IDCLK_P,
SPI4B_IDCLK_N, SPI4M_IDCLK_P and SPI4M_IDCLK_N). The source clock for the SPI-4 egress port is the internal SPI-4 clock generator.
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| IDT88P8341BHGI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT88P8341BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT88P8342BHGI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT88P8342BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT88P8344 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 |
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