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參數(shù)資料
| 型號(hào)： | IDT88K8483BRI |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 105/162頁(yè) |
| 文件大小： | 0K |
| 描述： | IC SPI-4 EXCHANGE 3PORT 672-BGA |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | * |
| 其它名稱： | 88K8483BRI |
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October 20, 2006
IDT IDT88K8483
Egress associated status channel
Bit alignment
The alignment selection is programed by AUTO_ALIGN flag in the SPI-4 Egress Automatic Alignment Control Register (p. 115).
The device is responsible for edge transition histogram for each lane. The data is sampled by 10-phased shifted clock during each clock cycle.
Each consecutive pairs of sampled values are XORed and accumulated during a fixed observation window to generate transition edge histogram.
The measure histogram is triggered by writing to the LANE field in the SPI-4 Histogram Measure Launch Register (p. 117). The measurement
process is indicated by a BUSY flag in the SPI-4 Histogram Measure Status Register (p. 117). The BUSY field is set to 1 when a measurement is
launched. The BUSY field is auto cleared to 0 when the measurement is finished. The status channel TAP is configured by the AUTO_ALIGN field in
The bit alignment sequence is as follows:
- Write lane number in the LANE field in the SPI-4 Histogram Measure Launch Register (p. 117).
- Poll the BUSY field in the SPI-4 Histogram Measure Status Register (p. 117). If BUSY is 0, then read the C[n] field in the SPI-4 Histogram Counter
Register (p. 117) which indicates the counter value. The counter value is used to select the tap.
- Write the selected Tap value to TAP field in the SPI-4 Bit Alignment Result Register (p. 118).
De-skew
The De-skew block can de-skew +/-1bit. For diagnostic purpose, an out of range offset between lines is provided. If deskew is more than 2 bits,
then the E_DSK_OOR field in the SPI-4 Egress Status Register (p. 115) is set. E_DSK_OOR field is cleared when in range.
Status Termination
The protocol (LVDS/LVTTL) is configured by SPI4_LVDSSTA input pin. The status channel has 2 states, IN_SYNCH and OUT_OF_SYNCH. A
number of consecutive DIP-2 error-free values cause a transition from OUT_OF_SYNCH to IN_SYNCH state. This number is configured by SPI-4
Egress Configuration Register (p. 113). A number of consecutive DIP-2 errors will force the machine to OUT_OF_SYNCH state. This number is
configured in the SPI-4 Egress Configuration Register (p. 113). In LVDS protocol mode, 12 consecutive “11” will force the machine to
OUT_OF_SYNCH state. In LVTTL protocol mode, 12 consecutive ‘11’ will force the machine to OUT_OF_SYNCH state. The machine’s state is indi-
cated by E_SYNCV field in the SPI-4 Egress Status Register (p. 115). Any transition on the E_SYNCV field is captured, and generates an interrupt if
enabled.
Figure 19 Status Channel State Machine
The device supports one or two sets of calendars. If E_CSW_EN field in the SPI-4 Egress Calendar Switch Control Register (p. 116) is set to 1,
then two sets of calendars mode are used. In this case, a calendar selection word must be placed following the framing bit.
If CAL_SEL field in the SPI-4 Egress Calendar Switch Control Register (p. 116) is cleared to 0, then the device selects calendar 0, and the selec-
tion word is fixed to 01b. If CAL_SEL field is set to 1, then the device selects calendar 1, and the selection word is fixed to 10b.
IN_SYNCH
A
A=a number consecutive DIP-2 error free
B=a number of consecutive DIP-2 error,training, port disabled or
reset
Out of
synch
B
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| IDT88P8342BHGI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT88P8342BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
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