參數(shù)資料
型號(hào)： IDT88K8483BRI
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 129/162頁
文件大?。?/td> 0K
描述： IC SPI-4 EXCHANGE 3PORT 672-BGA
標(biāo)準(zhǔn)包裝： 24
系列： *
其它名稱： 88K8483BRI
69 of 162
October 20, 2006
IDT IDT88K8483
Figure 35 External PMON Time Base
Clock
IDT88K8483 has three programmable clock generators (main, tributary A and tributary B). One clock generator (main) is type M and two clock
generators (tributary A and tributary B) are type T. There are three input clocks SPI4A_RCLK, SPI4B_RCLK and SPI4M_RCLK. Each one of the clock
inputs is a clock source to one of the three internal clock generators. The device also has 4 clock configuration signals (DIV4, SPI4A_CLK_SEL,
SPI4B_CLK_SEL, and SPI4M_CLK_SEL) for programing the clock generators. The clock generator type M includes the following blocks: Prescaler,
PLL and three independent dividers as described in Figure 36 Clock Generator Type M p.70. The clock generators type T include the
following blocks: Prescaler, PLL and two independent dividers as described in Figure 37 Clock Generator Type T p.70.
The external configuration signals SPI4A_CLK_SEL, SPI4B_CLK_SEL and SPI4M_CLK_SEL configure the Divider 1 frequency to divide by 2 or 8
as described in Table 9. The external signals SPI4A_CLK_SEL, SPI4B_CLK_SEL and SPI4M_CLK_SEL value are reflected by CK_SEL_A,
CK_SEL_B and CK_SEL_C fields in the Clock Control Input Status Register (p. 104). The external configuration signal DIV4 configures the prescaler
frequency to divide by 4 or 1 as described in Table 10. The external signal DIV4 value is reflected by DIV_FOUR field in the Clock Control Input
CKSEL
(external input signal:
SPI4A_CLK_SEL, SPI4B_CLK_SEL,
SPI4M_CLK_SEL)
EDCLK / ISCLK_T
(external output signals)
Operation Mode
0
plloclk / 2 (plloclk is internal signal)
Full rate
1
plloclk / 8 (plloclk is internal signal)
Quarter rate
Table 9 CLK_SEL signals configuration
DIV4
(external input signal)
pllrclk
(internal signal)
Operation Mode
0
RCLK / 1 (RCLK is external input signal:
SPI4A_RCLK, SPI4B_RCLK,
SPI4M_RCLK)
Full rate
1
RCLK / 4 (RCLK is external input signal:
SPI4A_RCLK, SPI4B_RCLK,
SPI4M_RCLK)
Quarter rate
Table 10 DIV4 signal configuration
Tim ebase trigger
TIM EBASE interrupt
3-4m s for PM ON updating
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