參數(shù)資料
型號： IDT88K8483BRI
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 9/162頁
文件大?。?/td> 0K
描述： IC SPI-4 EXCHANGE 3PORT 672-BGA
標準包裝： 24
系列： *
其它名稱： 88K8483BRI
106 of 162
October 20, 2006
IDT IDT88K8483
SPI-4 Interface Enable Register
SPI-4 Ingress Configuration Register
Field
Read /
Write
Bits
Length Reset
State
Description
SPI4_EN
R/W
0:0
1
0
This bit enables/disables the SPI-4 interface ingress path. The SPI-4 ingress path is
disabled during reset and while configuring the port and is then enabled for normal
use.
0: Disable.
1: Enable.
SPI4_PDN
R/W
0:1
1
0
SPI4 interface power down mode.
0:Power up.
1:Power down or disable the SPI4 LVDS I/O, except the clock.
Note:
(1) The SPI4 interface has to be configured before enabling the interface
Table 57
SPI-4 Interface Enable Register (Block Base= 0x0300, Register Offset=0x00)
Field
Read /
Write
Bits
Length Reset
State
Description
I_INSYNC_THR
R/W
0:0-0:4
5
0x1F
The number of consecutive error free DIP-4 that need to be detected before the
SPI-4 ingress data channel is synchronized. The actual number of error free DIP 4
that need to be detected is I_INSYNC_THR+1.
I_CLK_EDGE
R/W
0:5
1
Indicates the active edge of the status clock in LVTTL mode.
0:The status information is output at the rising edge of the status clock.
1:The status information is output at the falling edge of the status clock.
I_LOW
R/W
0:6
1
This bit should be set to ‘0’ or ‘1’depending on the frequency of the ingress status
clock output when the status channel is selected to run in LVDS mode (LVDS_STA
bit inTable 62 indicates a ‘1’)
0: ISCLK clock is higher than or equal to 200 MHz.
1: ISCLK clock is lower than 200 MHz.
Reserved
R
0:7
1
0
Reserved bits.
I_OUTSYNC_THR
R/W
1:0-1:3
4
0xF
Indicates the number of consecutive DIP4 errors that need to be detected before the
ingress data channel changes from in sync state to out of sync state
Note: Please refer to Figure 16 for an illustration of out of sync and in sync state.
Table 58
SPI-4 Ingress Configuration Register (Block Base=0x0300, Register Offset=0x01)
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IDT88P8341BHGI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
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