參數(shù)資料
型號: IDT88K8483BRI
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 155/162頁
文件大小: 0K
描述: IC SPI-4 EXCHANGE 3PORT 672-BGA
標(biāo)準(zhǔn)包裝: 24
系列: *
其它名稱: 88K8483BRI
92 of 162
October 20, 2006
IDT IDT88K8483
Microprocessor Mailbox Output FIFO Length Register
Microprocessor Mailbox Output FIFO Status Register
Embedded Processor State Register
Field
Read /
Write
Bits
Length Reset
State
Description
Length
R/W
0:0 - 0:5
6
0
The number of data bytes written to the “data” field in the Microprocessor Mailbox
Table 24 Microprocessor Mailbox Output FIFO Length Register
(Register Offset=0x13)
Field
Read /
Write
Bits
Length Reset
State
Description
OFIFO_STATUS
R
0:0
1
0
Indicates whether the host CPU(READ side) or IDT88K8483 (WRITE side) has con-
trol of OFIFO.
0: IDT88K8483 (WRITE side) has control of IFIFO.
1: Host CPU(READ side) has control of IFIFO.
Table 25 Microprocessor Mailbox Input FIFO Status Register
(Register Offset=0x15)
Field
Read /
Write
Bits
Length Reset
State
Description
EP_READY
R
0:0
1
0
This flag indicates whether the chip is ready to download the firmware binary file
from the host CPU. This flag is checked before the host CPU downloads to the
IDT88K8483. This bit is cleared by reset and will go high after the chip is initialized.
0:Not ready for download.
1:Ready for application s/w download.
EP_RUNNING
R
0:1
1
0
This flag indicates whether the downloading procedure is finished.
0:Download taking place.
1:Download finished.
CHIP_READY
R
0:2
1
0
This bit indicates that the downloaded software has initiated the chip and user can
access it. This bit is set by downloaded software and is cleared by reset.
0:Chip not yet ready.
1:Chip is ready to be used.
Table 26 Embedded Processor State Register
(Register Offset=0x16)
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