參數(shù)資料
型號(hào)： HDMP-1012
英文描述： Phase Lock Loop (PLL) IC; Number of Circuits:1; Package/Case:14-DIP; Mounting Type:Through Hole
中文描述： 4Low成本千兆速率發(fā)送/接收芯片組
文件頁(yè)數(shù)： 9/42頁(yè)
文件大?。?/td> 321K
代理商： HDMP-1012
581
Clock Select
The Clock Select accepts the
high speed digital signal from
the VCO and outputs an
internal high speed serial clock.
The VCO frequency is divided,
based on the DIV1/DIV0 inputs,
to the input signal’s frequency
range. The Clock Select output,
accessible through BCLK, is an
internal serial clock. It is phase
and frequency locked to the
incoming signal. This internal
serial clock is used by the Input
Sampler to sample the data. It
is also used by the Clock
Generator to generate the
recovered frame rate clock.
By setting TCLKSEL high, the
user may input an external high
speed serial clock at TCLK. The
Clock Select accepts this signal
and directly outputs it as the
internal serial clock.
Clock Generator
The Clock Generator accepts the
serial clock generated from the
Clock Select and generates the
frame rate clock, based on the
setting of M20SEL. If M20SEL
is asserted, the incoming
encoded data frame is expected
to be 24 bits wide (20 data bits
and 4 control bits). The master
transition in the control section
of encoded data stream is
expected every 24 bits, and used
to ensure proper frame syn-
chronization of the output frame
clock, STRBOUT.
Input Sampler
The serial input signal is
converted into a serial bit
stream, using the extracted
internal serial clock from the
Clock Select. This output is
sent to the frame demux.
Frame Demux
The Frame Demux demulti-
plexes the serial bit stream from
the Input Sampler into a 20 or
24 bit wide parallel data word,
based on the setting of M20SEL.
The most significant 4 bits are
sent to the C-Field Decoder,
while the remaining 16 or 20
bits are sent to the D-Field
Decoder.
C-Field Decoder
The C-Field Decoder accepts the
control information from the
Frame Demux and determines
what kind of frame is being
received and whether or not it
has to be inverted. The control
bits are sent to the State
Machine for error checking.
The decoded information is sent
to the D-Field Decoder. CAV* is
set low if the incoming frame is
control data. DAV* is set low if
the information is data. If
neither DAV* nor CAV* is set
low, then the incoming frame is
expected to be a fill frame. If
FLAGSEL is asserted, the
FLAG bit is restored to its
original form. Otherwise, FLAG
is used to differentiate between
the even and odd frames in
Double Frame Mode. For more
information about this, refer to
Double Frame Mode
.
D-Field Decoder
The D-Field Decoder accepts the
data field of the incoming data
frame from the Frame Demux.
Based on information from the
C-Field Decoder, which deter-
mines what type of data is being
received, the D-Field Decoder
restores the parallel data back
to its original form.
State Machine
The State Machine is used in
full duplex mode to perform the
functions of link startup, link
maintenance, and error check-
ing. By setting the SMRST0*
and SMRST1* low, the user,
too, can reset the state machine
and initiate link startup.
SMRST1* is usually connected
to the transmitters LOCKED
output. STAT1 and STAT0
denote the current state of link
during startup. ACTIVE is an
input normally driven by the
STAT1 and STAT0 outputs.
This ACTIVE input is retimed
by STRBOUT and presented to
the user as LINKRDY*.
LINKRDY* is an active low
output that indicates when the
link is ready to transmit data.
Refer to
The State Machine
Handshake Protocol
section on
page 600 for more details.
相關(guān)PDF資料
PDF描述
HDMP-1014 Bipolar Transistor; Collector Emitter Voltage, Vceo:400V; Transistor Polarity:N Channel; Power Dissipation:250W; C-E Breakdown Voltage:400V; DC Current Gain Min (hfe):10; Collector Current:50A; Package/Case:TO-3
HDMP-1022 Audio Power Amplifier; Speaker Channels:Mono; Headphone Channels:Mono; Output Power, Po:2W; Load Impedance Min:8ohm; Supply Voltage Max:24V; Supply Voltage Min:6V
HDMP-1024 Low Cost Gigabit Rate Receive Chip Set with TTL I/Os(帶TTL輸入/輸出的低價(jià)格千兆位速率接收芯片)
HDMP-1032 1.4 GBd Transmitter Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 傳送器)
HDMP-1034 1.4 GBd Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 接收器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HDMP-1014 制造商:Hewlett Packard Co 功能描述:
HDMP-1022 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Low Cost Gigabit Rate Transmit/Receive Chip Set with TTL I/Os
HDMP-1024 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Low Cost Gigabit Rate Transmit/Receive Chip Set with TTL I/Os
HDMP-1032 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate
HDMP-1032A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1.4 GBd Transmitter Chip with CIMT Encoder/Decoder and Variable Data Rate
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*