- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370499 > HDMP-1012 Phase Lock Loop (PLL) IC; Number of Circuits:1; Package/Case:14-DIP; Mounting Type:Through Hole PDF資料下載
參數(shù)資料
| 型號(hào)： | HDMP-1012 |
| 英文描述： | Phase Lock Loop (PLL) IC; Number of Circuits:1; Package/Case:14-DIP; Mounting Type:Through Hole |
| 中文描述： | 4Low成本千兆速率發(fā)送/接收芯片組 |
| 文件頁(yè)數(shù)： | 6/42頁(yè) |
| 文件大小： | 321K |
| 代理商： | HDMP-1012 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)當(dāng)前第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)
578
the transmitter. The clock
generator section performs the
clock multiplication to the
necessary serial clock rate.
By setting EHCLKSEL high, the
user may provide an external high
speed serial clock at STRBIN.
This clock is used directly by the
high speed serial circuitry to
output the serial data.
Control Logic and C-Field
Encoder
The Control Logic is responsible
for determining what information
is serially sent to the output. If
CAV* is low, it sends the data at
D0..D8 and D9..D17 as control
word information. If CAV* is high
and DAV* is low, it sends parallel
word data at the data inputs. If
neither CAV* nor DAV* is set low,
then the transmitter assumes the
link is not being used. In this
state, the control logic triggers
the Data Encoder to send Fill
Frames to maintain the link DC
balance and allow the receiver to
HDMP-1012 Tx Block
Diagram
The HDMP-1012 was designed to
accept 16 or 20 bit wide parallel
data and transmit it over a high
speed serial line, while minimizing
the user’s necessary interface to
the high speed circuitry. In order
to accomplish this task, the
HDMP-1012 performs the
following functions:
Parallel Word Input
High Speed Clock Multiplication
Frame Encoding
Parallel to Serial Multiplexing
PLL/Clock Generator
The Phase Lock-loop and Clock
Generator are responsible for
generating all internal clocks
needed by the transmitter to
perform its functions. These
clocks are based on a supplied
frame clock (STRBIN) and control
signals (M20SEL, MDFSEL,
EHCLKSEL, DIV1, DIV0). In
normal operation (MDFSEL=0),
STRBIN is expected to be the
incoming frame clock. The PLL/
Clock Generator locks on to this
incoming rate and multiplies the
clock up to the needed high speed
serial clock. Based on M20SEL,
which determines whether the
incoming data frame is 16 or 20
bits wide, the PLL/Clock
Generator multiplies the frame
rate clock by 20 or 24
respectively (data bits + 4 control
bits). DIV1/DIV0 are set to inform
the transmitter of the frequency
range of the incoming data
frames. The internal frame rate
clock is accessible through
STRBOUT and the high speed
serial clock is accessible through
HCLK.
When MDFSEL is set high, the
transmitter is in Double Frame
Mode. Using this option, the user
may send a 32 or 40 bit wide data
frame in two segments while
supplying the original 32 or 40 bit
frame clock at STRBIN. Doubling
of the frame rate is performed by
Figure 4. HDMP-1012 Transmitter Block Diagram.
ED
CONTROL
LOGIC
+
C-FIELD
ENCODER
FF
CAV*
DAV*
FLAG
D0-D19
RST*
D-FIELD
ENCODER
L
L
SIGN
FRAME
MUX
R
F
M
S
E
D
D
M
PLL / CLOCK
GENERATOR
A
OUTPUT
SELECT
CAP0
CAP1
0.1 μF
STRBOUT
HCLK
LOCKED
DOUT
LOUT
LOOPEN
INV
INTERNAL
CLOCKS
INPUT
LATCH
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HDMP-1014 | Bipolar Transistor; Collector Emitter Voltage, Vceo:400V; Transistor Polarity:N Channel; Power Dissipation:250W; C-E Breakdown Voltage:400V; DC Current Gain Min (hfe):10; Collector Current:50A; Package/Case:TO-3 |
| HDMP-1022 | Audio Power Amplifier; Speaker Channels:Mono; Headphone Channels:Mono; Output Power, Po:2W; Load Impedance Min:8ohm; Supply Voltage Max:24V; Supply Voltage Min:6V |
| HDMP-1024 | Low Cost Gigabit Rate Receive Chip Set with TTL I/Os(帶TTL輸入/輸出的低價(jià)格千兆位速率接收芯片) |
| HDMP-1032 | 1.4 GBd Transmitter Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 傳送器) |
| HDMP-1034 | 1.4 GBd Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 接收器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HDMP-1014 | 制造商:Hewlett Packard Co 功能描述: |
| HDMP-1022 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Low Cost Gigabit Rate Transmit/Receive Chip Set with TTL I/Os |
| HDMP-1024 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Low Cost Gigabit Rate Transmit/Receive Chip Set with TTL I/Os |
| HDMP-1032 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1032A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1.4 GBd Transmitter Chip with CIMT Encoder/Decoder and Variable Data Rate |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。