參數(shù)資料
型號： HDMP-1012
英文描述： Phase Lock Loop (PLL) IC; Number of Circuits:1; Package/Case:14-DIP; Mounting Type:Through Hole
中文描述： 4Low成本千兆速率發(fā)送/接收芯片組
文件頁數(shù)： 27/42頁
文件大?。?/td> 321K
代理商： HDMP-1012
599
HDMP-1014 (Rx)
Detectable Error States
M20SEL Not Asserted (16 bit mode)
D-Field
xx
xx
0x
11
xx
xx
C-Field
x00x
x11x
1100
1100
1010
0101
xxxxxxx
xxxxxxx
xxxxxxx
xxxxxxx
xxxxxxx
xxxxxxx
xxxxxxx
xxxxxxx
xxxxxxx
xxxxxxx
xxxxxxx
xxxxxxx
HDMP-1014 (Rx)
Detectable Error States
M20SEL Asserted (20 bit mode)
D-Field
xx
xx
0x
11
xx
xx
C-Field
x00x
x11x
1100
1100
1010
0101
xxxxxxxxx
xxxxxxxxx
xxxxxxxxx
xxxxxxxxx
xxxxxxxxx
xxxxxxxxx
xxxxxxxxx
xxxxxxxxx
xxxxxxxxx
xxxxxxxxx
xxxxxxxxx
xxxxxxxxx
Tx Operation Principles
The HDMP-1012 (Tx) is imple-
mented in a high performance
silicon bipolar process. The Tx
performs the following functions
for link operation:
Phase lock to frame rate clock
Clock multiplication
Frame encoding
Multiplexing
In normal operation, the Tx phase
locks to a user supplied frame
rate clock and multiplies the
frequency to produce the high
speed serial clock. When locked,
the Tx indicates that it is locked
by asserting the LOCKED output.
When the ED input is asserted,
the Tx asserts the RFD signal
indicating that it is now ready to
transmit data or control frames.
The Tx can accept either 16 or 17
bit wide parallel data and produce
a 20 bit frame. It also can accept
20 or 21 bit data and produce a
24 bit frame. Similarly, either 14
bit or 18 bit control words can be
transmitted in a 20 bit or 24 bit
frame respectively.
Tx Encoding
A simplified block diagram of the
transmitter is shown in Figure 4.
The PLL/Clock Generator locks
onto the incoming frame rate (or
one-half frame rate) clock and
multiplies it up to the serial clock
rate. It also generates all the
internal clock signals required by
the Tx chip.
The data inputs, D0-D19, as well
as the control signals; ED, FF,
DAV*, CAV*, and FLAG are
latched in on the rising edge of an
internally generated frame rate
clock. The data field is then
encoded depending on the state
of the control signals. At the same
time, the coding field is
generated. At this point, the entire
frame has been constructed in
parallel form and its sign is
determined. This frame sign is
compared with the accumulated
sign of previously transmitted bits
to decide whether to invert the
frame. If the sign of the current
frame is the same as the sign of
the previously transmitted bits,
then the frame is inverted. If the
signs are opposite, the frame is
not inverted. No inversion is
相關(guān)PDF資料
PDF描述
HDMP-1014 Bipolar Transistor; Collector Emitter Voltage, Vceo:400V; Transistor Polarity:N Channel; Power Dissipation:250W; C-E Breakdown Voltage:400V; DC Current Gain Min (hfe):10; Collector Current:50A; Package/Case:TO-3
HDMP-1022 Audio Power Amplifier; Speaker Channels:Mono; Headphone Channels:Mono; Output Power, Po:2W; Load Impedance Min:8ohm; Supply Voltage Max:24V; Supply Voltage Min:6V
HDMP-1024 Low Cost Gigabit Rate Receive Chip Set with TTL I/Os(帶TTL輸入/輸出的低價格千兆位速率接收芯片)
HDMP-1032 1.4 GBd Transmitter Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 傳送器)
HDMP-1034 1.4 GBd Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 接收器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HDMP-1014 制造商:Hewlett Packard Co 功能描述:
HDMP-1022 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Low Cost Gigabit Rate Transmit/Receive Chip Set with TTL I/Os
HDMP-1024 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Low Cost Gigabit Rate Transmit/Receive Chip Set with TTL I/Os
HDMP-1032 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate
HDMP-1032A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1.4 GBd Transmitter Chip with CIMT Encoder/Decoder and Variable Data Rate
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