- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370499 > HDMP-1012 Phase Lock Loop (PLL) IC; Number of Circuits:1; Package/Case:14-DIP; Mounting Type:Through Hole PDF資料下載
參數(shù)資料
| 型號： | HDMP-1012 |
| 英文描述： | Phase Lock Loop (PLL) IC; Number of Circuits:1; Package/Case:14-DIP; Mounting Type:Through Hole |
| 中文描述： | 4Low成本千兆速率發(fā)送/接收芯片組 |
| 文件頁數(shù)： | 29/42頁 |
| 文件大小： | 321K |
| 代理商： | HDMP-1012 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁當前第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁
601
The lock detect circuit samples
STRBIN with phase shifted
versions of STRBOUT. If the
samples are not the proper
values, the LOCKED signal goes
low and stays low for at least two
frames.
Rx Operation Principles
The HDMP-1014 (Rx) is
monolithically implemented in a
high performance 25 GHz
f
t
bipolar process. When properly
configured, the Rx can accept
20B/24B CIMT line code frames,
and then output parallel 16B/17B/
20B/21B Data Word or 14B/18B
Control Word. The Rx provides
the following functions for link
operation:
Clock recovery
Frame synchronization
Data recovery
Demultiplexing
Frame decoding
Frame error detection
Link state control
Rx Encoding
Figure 5 shows a simplified block
diagram of the receiver. The data
path consists of an Input Select,
an Input Sampler, a Frame
Demultiplexer, a Control Field (C-
Field) Decoder, and a Data Field
(D-Field) Decoder. An on-chip
phase-locked loop (PLL) is used
to extract timing reference from
the serial input (DIN or LIN). The
PLL includes a Phase-Frequency
Detector, a Loop Filter, and a
variable-frequency oscillator
(VCO). All the RX internal clock
signals are generated from a
Clock Generator. The Clock
Generator can be driven either by
internal VCO or external signal,
TCLK, depending on the Clock
Select configuration.
Integrated on the chip is a Link-
Control State Machine for link
status monitoring and link
startup. Figure 13 shows the
details of the Input Select. The
Input Select chooses either
nominal serial data (DIN) or
loopback (LIN) signal for the
Input Sampler’s input. If loopback
enable (LOOPEN) is asserted, the
LIN input is selected. Also
included in the Input Selector is
cable equalization circuitry. When
coaxial cable is used as the
transmission media, by setting
EQEN=1 (enable equalization),
the equalization circuitry is in the
DIN signal path and can
compensate for high-frequency
cable loss.
Because the Data Field of the
CIMT line code can be either 16-
bit or 20-bit wide, the width
selection for Rx is made by
setting the input pin M20SEL
(Figure 5). If M20SEL=1, then
the Rx is configured to accept
serial input with 20-bit data field,
i.e., 24 bits per frame. If M20SEL
= 0, 16-bit data field is selected.
HDMP-1014 (Rx) Phase-
Locked Loop
A more detailed block diagram for
the Rx phase-locked loop (PLL) is
shown in Figure 14. In the PLL,
the phase of the serial input, SIN,
is compared with synchronizing
signals from the internal clock
generator, using either a phase
detector or a frequency detector.
The frequency detector disable
signal, FDIS, selects which
detector to use. If synchronization
in a link is not yet established, the
HDMP-1012 (Tx) should send out
Fill Frame 0 (FF0) or Fill Frame 1
(FF1) to the remote Rx. By
setting FDIS=0, the Rx uses
Figure 13. HDMP-1014 (Rx) Input Selector.
CABLE EQ
1
0
EQEN
1
0
SIN
DIN
LIN
LOOPEN
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HDMP-1014 | Bipolar Transistor; Collector Emitter Voltage, Vceo:400V; Transistor Polarity:N Channel; Power Dissipation:250W; C-E Breakdown Voltage:400V; DC Current Gain Min (hfe):10; Collector Current:50A; Package/Case:TO-3 |
| HDMP-1022 | Audio Power Amplifier; Speaker Channels:Mono; Headphone Channels:Mono; Output Power, Po:2W; Load Impedance Min:8ohm; Supply Voltage Max:24V; Supply Voltage Min:6V |
| HDMP-1024 | Low Cost Gigabit Rate Receive Chip Set with TTL I/Os(帶TTL輸入/輸出的低價格千兆位速率接收芯片) |
| HDMP-1032 | 1.4 GBd Transmitter Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 傳送器) |
| HDMP-1034 | 1.4 GBd Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 接收器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HDMP-1014 | 制造商:Hewlett Packard Co 功能描述: |
| HDMP-1022 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Low Cost Gigabit Rate Transmit/Receive Chip Set with TTL I/Os |
| HDMP-1024 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Low Cost Gigabit Rate Transmit/Receive Chip Set with TTL I/Os |
| HDMP-1032 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1032A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1.4 GBd Transmitter Chip with CIMT Encoder/Decoder and Variable Data Rate |
發(fā)布緊急采購，3分鐘左右您將得到回復。