參數(shù)資料
型號(hào)： HDMP-1012
英文描述： Phase Lock Loop (PLL) IC; Number of Circuits:1; Package/Case:14-DIP; Mounting Type:Through Hole
中文描述： 4Low成本千兆速率發(fā)送/接收芯片組
文件頁(yè)數(shù)： 2/42頁(yè)
文件大?。?/td> 321K
代理商： HDMP-1012
574
and bit synchronization are
maintained. When data is not
available to send, the link
maintains synchronization by
transmitting fill frames. Two
(training) fill frames are reserved
for handshaking during link
startup.
User control space is also sup-
ported. If Control Available is
asserted at the Tx chip, the least
significant 14 or 18 bits of the
data are sent and the Rx Control
Available line will indicate the
data as a Control Word.
It is the intention of this data
sheet to provide the design
engineer all of the information
regarding the HDMP-1012/1014
chipset necessary to design this
product into their application. To
assist you in using this data sheet,
the following Table of Contents is
provided.
Table of Contents
Topic
Typical Applications ....................................................................... 575
Setting the Operating Rate ..............................................................576
Transmitter Block Diagram .............................................................578
Receiver Block Diagram ................................................................. 580
Transmitter Timing Characteristics ................................................ 582
Receiver Timing Characteristics ..................................................... 583
DC Electrical Specifications ........................................................... 584
AC Electrical Specifications ............................................................584
Typical Lock-Up Times ...................................................................584
Absolute Maximum Ratings ............................................................ 585
Thermal Characteristics ................................................................. 585
I/O Type Definitions ....................................................................... 585
Pin-Out Diagrams .......................................................................... 586
Transmitter Pin Definitions ............................................................ 587
Receiver Pin Definitions ................................................................. 591
Mechanical Dimensions and
Surface Mount Assembly Instructions ......................................... 595
Appendix I: Additional Internal
Architecture Information
........................................................596
Line Code Description .................................................................... 596
Data Frame Codes ......................................................................... 596
Control Frame Codes ..................................................................... 597
Fill Frame Codes ............................................................................ 598
Tx Operation Principles ................................................................. 599
Tx Encoding ..................................................................................599
Tx Phase Locked Loop ....................................................................600
Rx Operation Principles ................................................................. 601
Rx Encoding ...................................................................................601
HDMP-1014 (Rx) Phase Locked Loop ............................................601
HDMP-1014 (Rx) Decoding ............................................................602
HDMP-1014 (Rx) Link Control State
Machine Operation Principle .......................................................603
The State Machine Handshake Protocol ..........................................603
Appendix II: Link Configuration Examples
.............................605
Duplex/Simplex Configurations ...................................................... 605
Full Duplex .....................................................................................605
Simplex Method I: Simplex with Low Speed Return Path ...............606
Simplex Method II: Simplex with Periodic Sync Pulse ....................607
Simplex Method III: Simplex with
External Reference Oscillator ......................................................607
Data Interface for Single/Double Frame Mode ................................ 608
Single Frame Mode (MDFSEL=0) .................................................. 608
Double Frame Mode (MDFSEL=1) ................................................ 609
Supply Bypassing and Integrator Capacitor ....................................610
Integrating Capacitor ......................................................................610
Power Supply Bypassing and Grounding ........................................ 610
Electrical Connections ....................................................................611
I-ECL and O-ECL ............................................................................611
High Speed Interface: I-H50 & O-BLL ............................................612
TTL and Positive 5 V Operation ......................................................613
Mode Options ................................................................................. 614
Page
相關(guān)PDF資料
PDF描述
HDMP-1014 Bipolar Transistor; Collector Emitter Voltage, Vceo:400V; Transistor Polarity:N Channel; Power Dissipation:250W; C-E Breakdown Voltage:400V; DC Current Gain Min (hfe):10; Collector Current:50A; Package/Case:TO-3
HDMP-1022 Audio Power Amplifier; Speaker Channels:Mono; Headphone Channels:Mono; Output Power, Po:2W; Load Impedance Min:8ohm; Supply Voltage Max:24V; Supply Voltage Min:6V
HDMP-1024 Low Cost Gigabit Rate Receive Chip Set with TTL I/Os(帶TTL輸入/輸出的低價(jià)格千兆位速率接收芯片)
HDMP-1032 1.4 GBd Transmitter Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 傳送器)
HDMP-1034 1.4 GBd Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 接收器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HDMP-1014 制造商:Hewlett Packard Co 功能描述:
HDMP-1022 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Low Cost Gigabit Rate Transmit/Receive Chip Set with TTL I/Os
HDMP-1024 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Low Cost Gigabit Rate Transmit/Receive Chip Set with TTL I/Os
HDMP-1032 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate
HDMP-1032A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1.4 GBd Transmitter Chip with CIMT Encoder/Decoder and Variable Data Rate
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