參數(shù)資料
型號： HDMP-1012
英文描述： Phase Lock Loop (PLL) IC; Number of Circuits:1; Package/Case:14-DIP; Mounting Type:Through Hole
中文描述： 4Low成本千兆速率發(fā)送/接收芯片組
文件頁數(shù)： 1/42頁
文件大小： 321K
代理商： HDMP-1012
573
Low Cost Gigabit Rate
Transmit/Receive Chip Set
Technical Data
Features
Transparent, Extended
Ribbon Cable Replacement
Implemented in a Low Cost
Aluminum M-Quad 80
Package
High-Speed Serial Rate
150-
1500 MBaud
Standard 100K ECL
Interface
16, 17, 20, or 21 Bits Wide
Reliable Monolithic Silicon
Bipolar Implementation
On-chip Phase-Locked Loops
- Transmit Clock Generation
- Receive Clock Extraction
Applications
Backplane/Bus Extender
Video, Image Acquisition
Point to Point Data Links
Implement SCI-FI Standard
Implement Serial HIPPI
Specification
Description
The HDMP-1012 transmitter and
the HDMP-1014 receiver are used
to build a high speed data link for
point to point communication.
The monolithic silicon bipolar
transmitter chip and receiver chip
are each provided in a standard
aluminum M-Quad 80 package.
From the user’s viewpoint, these
products can be thought of as
providing a “virtual ribbon cable”
interface for the transmission of
data. Parallel data loaded into the
Tx (transmitter) chip is delivered
to the Rx (receiver) chip over a
serial channel, which can be
either a coaxial copper cable or
optical link.
The chip set hides from the user
all the complexity of encoding,
multiplexing, clock extraction,
demultiplexing and decoding.
Unlike other links, the phase-
locked-loop clock extraction
circuit also transparently provides
for frame synchronization - the
user is not troubled with the
periodic insertion of frame
synchronization words. In
addition, the dc balance of the
line code is automatically
maintained by the chip set. Thus,
the user can transmit arbitrary
data without restriction. The Rx
chip also includes a state-machine
controller (SMC) that provides a
startup handshake protocol for
the duplex link configuration.
The serial data rate of the T/R link
is selectable in four ranges (see
tables on page 5), and extends
from 120 Mbits/s up to 1.25
Gbits/s. The parallel data interface
is 16 or 20 bit single-ended ECL,
pin selectable. A flag bit is
available and can be used as an
extra 17th or 21st bit under the
user’s control. The flag bit can
also be used as an even or odd
frame indicator for dual-frame
transmission. If not used, the link
performs expanded error
detection.
The serial link is synchronous,
and both frame synchronization
HDMP-1012 Transmitter
HDMP-1014 Receiver
5962-0049E (6/94)
相關(guān)PDF資料
PDF描述
HDMP-1014 Bipolar Transistor; Collector Emitter Voltage, Vceo:400V; Transistor Polarity:N Channel; Power Dissipation:250W; C-E Breakdown Voltage:400V; DC Current Gain Min (hfe):10; Collector Current:50A; Package/Case:TO-3
HDMP-1022 Audio Power Amplifier; Speaker Channels:Mono; Headphone Channels:Mono; Output Power, Po:2W; Load Impedance Min:8ohm; Supply Voltage Max:24V; Supply Voltage Min:6V
HDMP-1024 Low Cost Gigabit Rate Receive Chip Set with TTL I/Os(帶TTL輸入/輸出的低價格千兆位速率接收芯片)
HDMP-1032 1.4 GBd Transmitter Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 傳送器)
HDMP-1034 1.4 GBd Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 接收器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HDMP-1014 制造商:Hewlett Packard Co 功能描述:
HDMP-1022 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Low Cost Gigabit Rate Transmit/Receive Chip Set with TTL I/Os
HDMP-1024 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Low Cost Gigabit Rate Transmit/Receive Chip Set with TTL I/Os
HDMP-1032 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate
HDMP-1032A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1.4 GBd Transmitter Chip with CIMT Encoder/Decoder and Variable Data Rate
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