參數(shù)資料
型號： GS4576S09L-25
廠商： GSI TECHNOLOGY
元件分類： DRAM
英文描述： DDR DRAM, PBGA144
封裝： UBGA-144
文件頁數(shù)： 56/64頁
文件大?。?/td> 2691K
代理商： GS4576S09L-25
Preliminary
GS4576S09/18L
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01 4/2011
6/64
2011, GSI Technology
Functional Block Diagram2
Ban
k0
row-
addres
s
latch
and
decoder
Column
Dec
oder
16,384
32
I/O
gati
ng
DQM
Mask
Logic
16,384
Bank
7
Bank
6
Bank
5
Bank
4
Ba
nk
3
Bank
2
Bank
1
Bank
0
Bank
0
mem
ory
array
(16,
384
x
32
x
16
x
9)
2
Sense
amplifiers
Read
Log
ic
Q
La
tch
QK
/Q
K
Gen
er
ator
Dr
iv
er
s
DL
L
CK/
C
K
RCV
RS
Wr
ite
FIF
O
and
Drivers
CLK
in
InputLog
ic
DK
/D
K
QK
0/Q
K0
QV
LD
ZQ
CAL
DM
D0–D8
Command
decod
e
O
D
Tcontrol
ZQ
CA
L
(0..
.8)
V
TT
R
TT
Ou
tput
d
riv
ers
Address
Re
gister
CK
A0–A21
1
BA
0–B
A2
ODT
control
Mode
Register
ZQ
31
9
2
9
Contr
ol
logic
Bank
Control
Logic
Co
lum
n-
address
counter/
lat
ch
Row-
address
MU
X
Refresh
Coun
ter
3
81
31
8
14
5
14
n
25
18
8
1
CK
WE
CS
REF
O
D
Tcontrol
V
TT
R
TT
28
8
288
Q
0–Q8
Notes: 1.
Example
for
BL
=
2;
column
address
wil
lbe
reduced
with
an
increase
in
burst
length.
2.
16
=
(length
of
burst)
x
2^(number
of
column
addresses
to
WRITE
FIFO
and
READ
logic).
3.
64M
x
9
drawing
shown
for
reference.
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GS54180RK 1 ELEMENT, 18 uH, GENERAL PURPOSE INDUCTOR, SMD
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