參數(shù)資料
型號: GS4576S09L-25
廠商: GSI TECHNOLOGY
元件分類: DRAM
英文描述: DDR DRAM, PBGA144
封裝: UBGA-144
文件頁數(shù): 26/64頁
文件大?。?/td> 2691K
代理商: GS4576S09L-25
Preliminary
GS4576S09/18L
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01 4/2011
32/64
2011, GSI Technology
MRS Command In Multiplexed Mode
The Mode Register Set command stores the data for controlling the RAM into the Mode Register. The register allows the user to
modify Read and Write pipeline length, burst length, test mode, and I/O options. The Multiplexed MRS command requires two
cycles to complete The Ax address is sampled on the true crossing of clock with the MRS Command. The Ay address and a
required NOP command are captured on the next next crossing of clock. After issuing a valid MRS command, tMRSC must be met
before any READ, WRITE, MRS, or AREF command can be issued to the LLDRAM II. This statement does not apply to the
consecutive MRS commands needed for internal logic reset during the initialization routine. The MRS command can only be issued
when all banks are idle and no bursts are in progress.
Note: The data written by the prior burst length is not guaranteed to be accurate when the burst length of the device is changed.
MRS Command in Multiplexed Mode
MRS
Ax
Ay
CK
CS
WE
REF
A(9:0)
A(18:10)
BA(2:0)
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