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參數(shù)資料
| 型號： | GS4576S09L-25 |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | DDR DRAM, PBGA144 |
| 封裝： | UBGA-144 |
| 文件頁數(shù)： | 48/64頁 |
| 文件大?。?/td> | 2691K |
| 代理商： | GS4576S09L-25 |
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Preliminary
GS4576S09/18L
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01 4/2011
52/64
2011, GSI Technology
Read Burst Timing
Q0
Q1
Q2
Q3
tDVW
tQKQmin
tQKQmax
tQKVLD
tQKH
tQKL
tCKQK
tCK
tCKL
tCKH
CK
QKx
QVLD
Q
IEEE 1149.1 Serial Boundary Scan (JTAG)
LLDRAM II includes an IEEE 1149.1 (JTAG) serial boundary scan Test Access Port (TAP). JTAG ports are generally used to
verify the connectivity of the device once it has been mounted on a Printed Circuit Board (PCB). The port operates in accordance
with IEEE Standard 1149.1-2001 (JTAG). Because the ZQ pin is actually an analog output, to ensure proper boundary-scan testing
of the ZQ pin, Mode Register Bit 8 (M8) needs to be set to 0 until the JTAG testing of the pin is complete. Note that upon power
up, the default state of Mode Register Bit 8 (M8) is Low.
Whenever the JTAG port is used prior to the initialization of the LLDRAM II device, such as when initial conectivity testing is
conducted, it is critical that the CK and CK pins meet VID(DC) or that CS be held High from power-up until testing begins. Failure
to do so can result in inadvertent MRS commands being loaded and causing unexpected test results. Alternately a partial
initialization can be conducted that consists of simply loading a single MRS command with desired MRS Register settings. JTAG
testing may then begin as soon as tMRSC is satisfied. JTAG testing can be conducted after full initilization as well.
The input signals of the test access port (TDI, TMS, and TCK) are referenced to the VDD as a supply, while the output driver of the
TAP (TDO) is powered by VDDQ.
The JTAG test access port incorporates a standardTAP controller from which the Instruction Register, Boundary Scan Register,
Bypass Register, and ID Code Register can be selected. Each of these functions of the TAP controller are described below.
Disabling the JTAG Feature
Use of the JTAG port is never required for RAM operation. To disable the TAP controller, TCK must be tied Low (VSS) to prevent
clocking of the device. TDI and TMS are internally pulled up and may be unconnected or they can be connected to VDD directly or
through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state, which will not
interfere with the operation of the device.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK.
All of the states in the TAP Controller State Diagram are entered through the serial input of the TMS pin. A “0” in the diagram
represents a Low on the TMS pin during the rising edge of TCK while a “1” represents a High on TMS.
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